公开(公告)号：US10712955B2

公开(公告)日：2020-07-14

申请号：US16145772

申请日：2018-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-chang Jeon ,  Sang-won Park ,  Dong-kyo Shim ,  Dong-hun Kwak

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.

公开(公告)号：US20180211705A1

公开(公告)日：2018-07-26

申请号：US15793221

申请日：2017-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kyo Shim ,  Sang-won Park ,  Su-chang Jeon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C11/56 ,  G11C11/4094

CPC classification number: G11C16/0483 ,  G11C11/4094 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3427

Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.

公开(公告)号：US10325657B2

公开(公告)日：2019-06-18

申请号：US15793221

申请日：2017-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kyo Shim ,  Sang-won Park ,  Su-chang Jeon

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C11/4094 ,  G11C16/26 ,  G11C16/30 ,  G11C11/56 ,  G11C16/24

Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.

公开(公告)号：US20190295651A1

公开(公告)日：2019-09-26

申请号：US16441145

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kyo Shim ,  Sang-won Park ,  Su-chang Jeon

IPC: G11C16/04 ,  G11C16/24 ,  G11C11/56 ,  G11C16/30 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/4094 ,  G11C16/08

Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.

公开(公告)号：US20190114099A1

公开(公告)日：2019-04-18

申请号：US16145772

申请日：2018-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-chang JEON ,  Sang-won Park ,  Dong-kyo Shim ,  Dong-hun Kwak

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.