公开(公告)号：US20190057742A1

公开(公告)日：2019-02-21

申请号：US15955029

申请日：2018-04-17

Applicant: Samsung Electronics Co, Ltd

Inventor： Su-chang JEON ,  Kui-han Ko ,  Dong-hun Kwak ,  Jin-young Kim

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04 ,  H01L27/11582

Abstract: Provided is a method performed by a nonvolatile memory device, the method may include: initiating a first program operation corresponding to a first program loop among a plurality of program loops; receiving a suspend command for an urgent read operation during the first program operation; determining a recovery timing from either of a first timing contemporaneous with the receiving the suspend command, and a second timing after completion of the first program operation, based on the suspend command; and initiating a recovery at the determined recovery timing by applying a recovery voltage to a selected word line.

公开(公告)号：US20240078034A1

公开(公告)日：2024-03-07

申请号：US18506293

申请日：2023-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G11C7/1063 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C16/0483

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

公开(公告)号：US20180052639A1

公开(公告)日：2018-02-22

申请号：US15678759

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-jin LEE ,  Su-chang JEON

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G11C7/1063 ,  G11C7/20 ,  G11C7/22 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/32

Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

公开(公告)号：US20190114099A1

公开(公告)日：2019-04-18

申请号：US16145772

申请日：2018-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-chang JEON ,  Sang-won Park ,  Dong-kyo Shim ,  Dong-hun Kwak

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.

公开(公告)号：US20210294517A1

公开(公告)日：2021-09-23

申请号：US17231734

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C7/10

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

公开(公告)号：US20190324679A1

公开(公告)日：2019-10-24

申请号：US16503116

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/20 ,  G11C7/20 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.