公开(公告)号：US20250148046A1

公开(公告)日：2025-05-08

申请号：US18830101

申请日：2024-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIHA KIM ,  DONGJIN LEE ,  JUNHWAN LEE ,  YONGDEOK KIM ,  GEUNTAE BAE

IPC: G06F17/14

Abstract: A method of performing a fast Fourier transform (FFT) operation for a plurality of input values includes generating a plurality of sub-input data sets based on a plurality of input values, each having an index in a first dimension and an index in a second dimension, calculating a plurality of intermediate values by performing an FFT on each of the plurality of sub-input data sets, calculating partial FFT values for the plurality of input values based on the plurality of intermediate values, and generating a plurality of FFT value sets for the plurality of input values based on the partial FFT values.

公开(公告)号：US20240276729A1

公开(公告)日：2024-08-15

申请号：US18511597

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGMIN CHOI ,  HYUNMIN KIM ,  JUNTAEK PARK ,  DONGJIN LEE ,  RYOONGBIN LEE ,  JUNHEE LIM

IPC: H10B43/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate, a transistor disposed on the first substrate, and a first interconnection layer connected to the transistor. The first interconnection layer includes a first conductive line, a second conductive line, and a third conductive line, which are spaced apart from each other in a first direction parallel to a top surface of the first substrate. The second conductive line is disposed between the first conductive line and the third conductive line. A top surface of the second conductive line is located at a height higher than top surfaces of the first and third conductive lines with respect to the top surface of the first substrate.

公开(公告)号：US20250022798A1

公开(公告)日：2025-01-16

申请号：US18441071

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HAKSEON KIM ,  DONGJIN LEE ,  JAEDUK LEE ,  KANG-OH YUN

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: According to an aspect of the present disclosure, a semiconductor device includes a peripheral structure, and a cell structure stacked on the peripheral structure. The cell structure includes a first substrate including a pad region and a cell region including a cell array region and an extending region, wherein the first substrate includes a first surface and a second surface opposite to the first surface, and wherein second surface faces the peripheral structure, a gate stacking structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the second surface of the first substrate, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes and the plurality of interlayer insulating layers, a plurality of gate contacts disposed on the extending region and connected to the plurality of gate electrodes, respectively, a cell insulation layer positioned over the second surface of the first substrate and covering the gate stacking structure, and an input/output contact disposed on the pad region and penetrating the cell insulation layer. The peripheral structure includes a second substrate electrically connected to the first substrate, a plurality of circuit elements positioned on the second substrate, a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers, a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers, a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers, and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements. In at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.

公开(公告)号：US20210118890A1

公开(公告)日：2021-04-22

申请号：US17137684

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US20250081467A1

公开(公告)日：2025-03-06

申请号：US18809742

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGJIN LEE ,  JAEDUK LEE ,  HAKSEON KIM ,  NAKJIN SON ,  KANG-OH YUN

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a plurality of transistors, a plurality of isolation portions, and a recess insulator. The semiconductor substrate includes a first transistor region and a second transistor region. The plurality of transistors includes a first transistor in the first transistor region and a second transistor in the second transistor region having larger operating voltage than the first transistor. Each isolation portion is at a boundary of a respective transistor of the plurality of transistors at a first surface of the semiconductor substrate. The recess insulator is disposed in the second transistor region at a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate.

公开(公告)号：US20250048638A1

公开(公告)日：2025-02-06

申请号：US18432459

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAKSEON KIM ,  KANG-OH YUN ,  DONGJIN LEE ,  YOUNGROK KIM ,  RYOONGBIN LEE ,  JAEDUK LEE

IPC: H10B43/40 ,  G11C16/24 ,  H10B43/27

Abstract: Disclosed are a semiconductor device and an electronic system including the semiconductor device. The semiconductor device includes a semiconductor substrate including a plurality of trenches and silicon, a gate electrode positioned on the semiconductor substrate and between the trenches, and a source region and a drain region respectively positioned within the trenches. The source region and the drain region include silicon carbide (SiC) or gallium nitride (GaN), the source region and the drain region each includes a first lightly doped region and a second lightly doped region, and a whole of the first lightly doped region overlaps the second lightly doped region in a direction perpendicular to an upper surface of the semiconductor substrate.

公开(公告)号：US20200083229A1

公开(公告)日：2020-03-12

申请号：US16520730

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4091

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.