公开(公告)号：US20210174001A1

公开(公告)日：2021-06-10

申请号：US17022233

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G06F30/392 ,  G06F30/398 ,  G03F1/36

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20240265188A1

公开(公告)日：2024-08-08

申请号：US18641386

申请日：2024-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  Bonghyun Lee

IPC: G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20220215153A1

公开(公告)日：2022-07-07

申请号：US17702879

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G03F1/36 ,  G06F30/398 ,  G06F30/392

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20250148046A1

公开(公告)日：2025-05-08

申请号：US18830101

申请日：2024-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIHA KIM ,  DONGJIN LEE ,  JUNHWAN LEE ,  YONGDEOK KIM ,  GEUNTAE BAE

IPC: G06F17/14

Abstract: A method of performing a fast Fourier transform (FFT) operation for a plurality of input values includes generating a plurality of sub-input data sets based on a plurality of input values, each having an index in a first dimension and an index in a second dimension, calculating a plurality of intermediate values by performing an FFT on each of the plurality of sub-input data sets, calculating partial FFT values for the plurality of input values based on the plurality of intermediate values, and generating a plurality of FFT value sets for the plurality of input values based on the partial FFT values.

公开(公告)号：US20230169333A1

公开(公告)日：2023-06-01

申请号：US17862881

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGIN CHOI ,  Gunhee KIM ,  YONGDEOK KIM ,  MYEONG WOO KIM ,  SEUNGWON LEE ,  NARANKHUU TUVSHINJARGAL

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: Disclosed are a training method and apparatus for distributed training of a neural network, the training apparatus including processors configured to perform distributed training, wherein each of the processors is further configured to perform a forward direction operation for layers of the neural network, determine a loss of the neural network based on the forward direction operation, determine a local gradient for each layer of the neural network by performing a backward direction operation for the layers of the neural network based on the loss, determine whether to perform gradient clipping for a local gradient determined for a previous layer, in response to determining a local gradient for a current layer through the backward direction operation, determine an aggregated gradient based on the backward direction operation and the gradient clipping performed by each of the processors, and update parameters of the neural network based on the aggregated gradient.