公开(公告)号：US20210151101A1

公开(公告)日：2021-05-20

申请号：US17036004

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  CHEONAN LEE ,  SATORU YAMADA ,  JUNHEE LIM

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

公开(公告)号：US20240276729A1

公开(公告)日：2024-08-15

申请号：US18511597

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGMIN CHOI ,  HYUNMIN KIM ,  JUNTAEK PARK ,  DONGJIN LEE ,  RYOONGBIN LEE ,  JUNHEE LIM

IPC: H10B43/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate, a transistor disposed on the first substrate, and a first interconnection layer connected to the transistor. The first interconnection layer includes a first conductive line, a second conductive line, and a third conductive line, which are spaced apart from each other in a first direction parallel to a top surface of the first substrate. The second conductive line is disposed between the first conductive line and the third conductive line. A top surface of the second conductive line is located at a height higher than top surfaces of the first and third conductive lines with respect to the top surface of the first substrate.

公开(公告)号：US20190139983A1

公开(公告)日：2019-05-09

申请号：US16168219

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  BYOUNG-TAEK KIM ,  TAE HUN KIM ,  DONGKYUN SEO ,  JUNHEE LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20240276723A1

公开(公告)日：2024-08-15

申请号：US18463500

申请日：2023-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGBOK LEE ,  JUNHEE LIM

IPC: H10B43/27 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

公开(公告)号：US20200258905A1

公开(公告)日：2020-08-13

申请号：US16856663

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  BYOUNG-TAEK KIM ,  TAE HUN KIM ,  DONGKYUN SEO ,  JUNHEE LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.