公开(公告)号：US20230232640A1

公开(公告)日：2023-07-20

申请号：US17931116

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO LEE ,  DONGHO AHN ,  DONGGEON GU ,  WONJUN PARK ,  CHANGYUP PARK

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L45/1683

Abstract: A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.

公开(公告)号：US20250081865A1

公开(公告)日：2025-03-06

申请号：US18818913

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINWOO LEE ,  Hyunsang Hwang ,  Youngdong Kim ,  DONGHO AHN ,  Jin Myung Choi ,  Geon Hui Han

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.

公开(公告)号：US20200075850A1

公开(公告)日：2020-03-05

申请号：US16459637

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： JEONGHEE PARK ,  JIHO PARK ,  CHANGYUP PARK ,  DONGHO AHN

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.