公开(公告)号：US11626420B2

公开(公告)日：2023-04-11

申请号：US17178495

申请日：2021-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

公开(公告)号：US20180138188A1

公开(公告)日：2018-05-17

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L27/11534 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L27/11524

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US10825830B2

公开(公告)日：2020-11-03

申请号：US16392958

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Chul Jung ,  Bong-Tae Park ,  Jae-Joo Shim

IPC: H01L23/528 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768

Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

公开(公告)号：US10083978B2

公开(公告)日：2018-09-25

申请号：US15867974

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/1157 ,  H01L27/11534 ,  H01L27/11524 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  Y02E10/50

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20180061843A1

公开(公告)日：2018-03-01

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US10957708B2

公开(公告)日：2021-03-23

申请号：US16520979

申请日：2019-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

公开(公告)号：US09905569B1

公开(公告)日：2018-02-27

申请号：US15472720

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Won Kim ,  Bong-Tae Park ,  Ho-Jun Seong ,  Jae-Hwang Sim ,  Jung-Hoon Jun

IPC: H01L21/8234 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/265 ,  H01L21/027 ,  H01L27/11573 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11534

CPC classification number: H01L27/1157 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

公开(公告)号：US20210202520A1

公开(公告)日：2021-07-01

申请号：US17178495

申请日：2021-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.