Thin film transistor substrate
    1.
    发明授权
    Thin film transistor substrate 有权
    薄膜晶体管基板

    公开(公告)号:US09502579B2

    公开(公告)日:2016-11-22

    申请号:US14717734

    申请日:2015-05-20

    Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

    Abstract translation: 薄膜晶体管基板包括设置在基板上的栅电极; 半导体层,其设置在与所述栅电极部分重叠并且包括氧化物半导体材料的所述基板上; 以及设置在半导体层上的源电极和漏电极,其中漏电极与源电极间隔开。 源电极和漏极各自包括阻挡层和主布线层,主布线层设置在阻挡层上,阻挡层包括设置在半导体层上的第一金属层和第二金属层 设置在第一金属层上。

    DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME 有权
    显示装置及其制造方法

    公开(公告)号:US20150070643A1

    公开(公告)日:2015-03-12

    申请号:US14195051

    申请日:2014-03-03

    Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

    Abstract translation: 显示装置包括:限定晶体管和布线区域的基板; 晶体管区域中的薄膜晶体管,并且包括栅电极,有源层以及源极和漏极; 晶体管区域中的防蚀层,在布线区域中不存在并覆盖有源层,以及限定在防蚀层中的第一和第二接触孔,有源层电耦合到源电极和漏电极; 布线区域中的第一布线层; 覆盖所述栅电极和所述第一布线层的第一绝缘层和限定在所述布线区域中的所述第一绝缘层中的第三接触孔,并暴露所述第一布线层; 以及在所述第一绝缘层和所述布线区域中的第二布线层,并且经由所述第三接触孔电耦合到所述第一布线层。

    Display apparatus and method of manufacturing the same
    7.
    发明授权
    Display apparatus and method of manufacturing the same 有权
    显示装置及其制造方法

    公开(公告)号:US09236401B2

    公开(公告)日:2016-01-12

    申请号:US14195051

    申请日:2014-03-03

    Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

    Abstract translation: 显示装置包括:限定晶体管和布线区域的基板; 晶体管区域中的薄膜晶体管,并且包括栅电极,有源层以及源极和漏极; 晶体管区域中的防蚀层,在布线区域中不存在并覆盖有源层,以及限定在防蚀层中的第一和第二接触孔,有源层电耦合到源电极和漏电极; 布线区域中的第一布线层; 覆盖所述栅电极和所述第一布线层的第一绝缘层和限定在所述布线区域中的所述第一绝缘层中的第三接触孔,并暴露所述第一布线层; 以及在所述第一绝缘层和所述布线区域中的第二布线层,并且经由所述第三接触孔电耦合到所述第一布线层。

    Display substrate and method of manufacturing the same
    8.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号:US09064750B2

    公开(公告)日:2015-06-23

    申请号:US13869697

    申请日:2013-04-24

    CPC classification number: H01L27/124 G02F1/133707 H01L27/1248 H01L27/1288

    Abstract: A method of manufacturing a display substrate includes forming a gate insulation layer on the base substrate on which a gate metal pattern, forming a data metal pattern on the gate insulation layer, sequentially forming a insulation layer and an organic layer on the base substrate on which the data metal pattern is formed, partially exposing the organic layer, developing the organic layer to partially remove the organic layer on the data metal pattern and to expose at least a portion of the protecting layer on the gate metal pattern, forming a common electrode on the organic layer, forming a pixel electrode on the on the organic layer, and forming an insulation layer between the pixel electrode and the common electrode. An etching degree of a data metal may be controlled by controlling a thickness of a remained organic layer to reduce a damage of the data metal.

    Abstract translation: 一种制造显示基板的方法包括在基底基板上形成栅极绝缘层,栅基金属图案在栅绝缘层上形成数据金属图案,在基底基板上依次形成绝缘层和有机层, 形成数据金属图案,部分地暴露有机层,显影有机层以部分地去除数据金属图案上的有机层,并暴露栅极金属图案上的保护层的至少一部分,形成公共电极 有机层,在有机层上形成像素电极,在像素电极和公共电极之间形成绝缘层。 可以通过控制剩余的有机层的厚度来减少数据金属的损伤来控制数据金属的蚀刻程度。

    Display substrate comprising a plurality of conductive patterns

    公开(公告)号:US10446587B2

    公开(公告)日:2019-10-15

    申请号:US15594325

    申请日:2017-05-12

    Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

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