Abstract:
A data processing device, which processes and provides data to a plurality of logical pixels of a display device, includes: a data analysis part which analyzes information of text, color, line or edge in each of the data; and a data compensation part which compensates text data corresponding to a logical pixel which does not express text color among the data having the information of text based on the information analyzed in the data analysis part, where each of the logical pixels of the display device comprises at least one of red, green, blue and optional color sub-pixels.
Abstract:
A display device includes an interface, a power supply, a switch arrangement, and a display. The interface is driven by driving power and receives image data from an external source. The power supply generates first and second power based on a first input power in a first mode and delivers the driving power to the interface in the first mode. The switch arrangement forms a first delivery path to deliver the first power from the power supply to the interface in the first mode The display receives the second power from the power supply when driven in the first mode and receives the image data from the interface. The switch arrangement forms a second delivery path to deliver second input power to the power supply in a second mode when the interface receives the second input power from the external source in the second mode.
Abstract:
A display apparatus includes a display panel including a first pixel configured to include first and second sub-pixels and a second pixel configured to include third and fourth sub-pixels. A timing controller generates pixel data including first and second pixel data respectively corresponding to the first and second pixels and representable in a second matrix space, from pixel signals including first and second pixel signals representable in a first matrix space to respectively correspond to the first and second pixels. The timing controller generates the second pixel data on the basis of the first pixel signal adjacent to the second pixel signal which correspond to each second pixel data in the column direction in the first matrix space.
Abstract:
According to an embodiment, a display apparatus includes gate lines extending in a first direction, data lines extending in a second direction crossing the first direction, and pixels connected to the gate lines and the data lines. The pixels include pixels arranged in a k-th row and pixels arranged in a (k+1)th row disposed adjacent to the pixels arranged in the k-th row in the second direction. An (i+1)th gate line is disposed between the pixels in the k-th row and the pixels in the (k+1)th row. A first pixel arranged in a g-th column among the pixels arranged in the k-th row and a second pixel arranged in the g-th column among the pixels arranged in the (k+1)th row are connected to a j-th data line. The pixels arranged in the k-th row are alternately connected to an i-th gate line and the (i+1)th gate line.
Abstract:
A display device includes a timing controller and a display. The timing controller is connected to a connector of a USB cable and receive image signals from a host through the USB cable. The display receives the image signals from the timing controller to display an image. The timing controller includes an interface controller, a control signal selector, a data transmitter, and a data processor. The interface controller outputs control signals to control an output order of the image signals. The control signal selector selects and outputs a control signal corresponding to a connection position of the connector from the interface controller. The data transmitter determines the output order of the image signals from the host based on the control signal from the control signal selector. The data processor receives the image signal from the data transmitter and provides the image signal to the display.
Abstract:
An image processing circuit includes a mapper configured to convert an image signal into an intermediate data signal, and a renderer configured to convert the intermediate data signal into a data signal, wherein the renderer includes a memory configured to store the intermediate data signal and a flag signal, and a rendering circuit configured to output a data signal corresponding to a current line in response to a next intermediate data signal corresponding to a next line, to output a current intermediate data signal corresponding to the current line from the memory, and to output a previous flag signal corresponding to a previous line from the memory.
Abstract:
A display apparatus includes gate lines extending in a first direction, data lines extending in a second direction crossing the first direction, first color pixels, and second color pixels. A first color pixel arranged in an f-th column between an f-th data line and an (f+1)th data line is connected to one of the f-th data line and the (f+1)th data line. A first color pixel arranged in a g-th column between a g-th data line and a (g+1)th data line is connected to one of a (g−1)th data line and a (g+2)th data line. First color pixels in a first color pixel diagonal group receive data voltages having a same polarity.Second color pixels in a second color pixel diagonal group receive data voltages having a same polarity.
Abstract:
Provided is a display apparatus including a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixels and a plurality of sub-pixels. Two pixels among the pixels include five sub-pixels and temporally share a third sub-pixel among the five sub-pixels. The timing controller includes a filter that is set based on a region having the same area as four sub-pixels. The timing controller generates RGBW data having red, green, blue, and white data based on input data, and applies the filter to the RGBW data to generate output data corresponding to each of the sub-pixels.
Abstract:
A display apparatus includes a liquid crystal panel including gate lines, data lines, and pixels, a gate driver, a data driver, and a timing controller. The pixels include first and second pixels. The first and second pixels are arranged in pixel rows adjacent to each other, arranged in different pixel columns, connected to the same gate line, display the same color, and receive data voltages having different polarities from each other. The image data include first pixel data displayed in the first pixels and second pixel data displayed in the second pixels. When the first pixel data have a first grayscale value and the second pixel data have a second grayscale value different from the first grayscale value, the timing controller modulates the first and second pixel data to allow the first and second pixel data to have a grayscale value between the first and second grayscale values.
Abstract:
A display device according to the present disclosure includes a plurality of gate lines extending in a row direction, a plurality of data lines intersecting with the gate lines, the data lines extending in a column direction, a plurality of pixels connected to the gate lines and the data lines, and a data driving unit configured to output a plurality of data voltages to the pixels, wherein the data driving unit outputs the data voltages based on a first column inversion scheme and a second column inversion scheme to respective data lines along the column direction.