Abstract:
A display apparatus includes gate lines extending in a first direction, data lines extending in a second direction crossing the first direction, and pixels connected to the gate lines and the data lines. The pixels include pixels arranged in a k-th column between a k-th data line and a (k+1)th data line. The pixels arranged in the k-th column are arranged in a plurality of groups, and each of the groups includes 2i first pixels connected to the k-th data line and 2i second pixels connected to the (k+1)th data line. Successive ones of the pixels in each group are connected to the k-th data line and the (k+1)th data line in alternating manner.
Abstract:
A display apparatus includes a display panel including a first pixel configured to include first and second sub-pixels and a second pixel configured to include third and fourth sub-pixels. A timing controller generates pixel data including first and second pixel data respectively corresponding to the first and second pixels and representable in a second matrix space, from pixel signals including first and second pixel signals representable in a first matrix space to respectively correspond to the first and second pixels. The timing controller generates the second pixel data on the basis of the first pixel signal adjacent to the second pixel signal which correspond to each second pixel data in the column direction in the first matrix space.
Abstract:
A display apparatus includes a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixel groups. Each of the pixel groups includes a first pixel and a second pixel disposed adjacent to the first pixel. The first and second pixels together include n (n is an odd number equal to or greater than 3) sub-pixels. The first and second pixels share their collective {(n+1)/2}th sub-pixel.
Abstract:
A display apparatus includes a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixel groups. Each of the pixel groups includes a first pixel and a second pixel disposed adjacent to the first pixel. The first and second pixels together include n (n is an odd number equal to or greater than 3) sub-pixels. The first and second pixels share their collective {(n+1)/2}th sub-pixel.
Abstract:
A display apparatus includes first-kind data lines and second-kind data lines. Each of the first-kind data lines is connected to one of two pixels arranged in a k-th pixel row and a (k+1)th pixel row. Each of the second-kind data lines is connected to two pixels arranged in different pixel columns in the k-th pixel row and the (k+1)th pixel row. At least two first-kind data lines are consecutively arranged.
Abstract:
Provided is a display apparatus including a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a plurality of pixels and a plurality of sub-pixels. Two pixels among the pixels include five sub-pixels and temporally share a third sub-pixel among the five sub-pixels. The timing controller includes a filter that is set based on a region having the same area as four sub-pixels. The timing controller generates RGBW data having red, green, blue, and white data based on input data, and applies the filter to the RGBW data to generate output data corresponding to each of the sub-pixels.
Abstract:
A display apparatus includes a liquid crystal panel including gate lines, data lines, and pixels, a gate driver, a data driver, and a timing controller. The pixels include first and second pixels. The first and second pixels are arranged in pixel rows adjacent to each other, arranged in different pixel columns, connected to the same gate line, display the same color, and receive data voltages having different polarities from each other. The image data include first pixel data displayed in the first pixels and second pixel data displayed in the second pixels. When the first pixel data have a first grayscale value and the second pixel data have a second grayscale value different from the first grayscale value, the timing controller modulates the first and second pixel data to allow the first and second pixel data to have a grayscale value between the first and second grayscale values.