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公开(公告)号：US12237820B2
公开(公告)日：2025-02-25
申请号：US15687475
申请日：2017-08-26
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Yan Yan , Junhyung Lee
IPC: H03H11/24 , H03F1/02 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/72 , H03G1/00 , H03G3/30 , H03H7/25 , H04B1/40
Abstract: Attenuators having phase shift and gain compensation circuits. In some embodiments, a radio-frequency (RF) attenuator circuit can include one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path. The RF attenuator circuit can further include a global bypass path implemented between the input node and the output node. The RF attenuator circuit can further include a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
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公开(公告)号：US12074573B2
公开(公告)日：2024-08-27
申请号：US18482240
申请日：2023-10-06
Applicant: Skyworks Solutions, Inc.
Inventor： Aravind Kumar Padyana , Rimal Deep Singh , Junhyung Lee , Bipul Agarwal
CPC classification number: H03F3/189 , H04B1/16 , H03F2200/294 , H03F2200/451
Abstract: Multi-mode broadband low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes a first amplification stage and a second amplification stage having a lower gain than the first amplification stage. The LNA is operable in a plurality of operating modes including a first mode in which the first amplification stage and the second amplification stage operate in a cascade to amplify a radio frequency (RF) receive signal, and a second mode in which the first amplification stage amplifies the RF receive signal and the second amplification stage is bypassed.
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公开(公告)号：US20240097624A1
公开(公告)日：2024-03-21
申请号：US18240651
申请日：2023-08-31
Applicant: Skyworks Solutions, Inc.
Inventor： Bumkyum Kim , Yan Yan , Junhyung Lee
CPC classification number: H03F3/193 , H03F1/26 , H04B1/0475 , H03F2200/294 , H03F2200/451
Abstract: Radio frequency (RF) amplifiers with capacitance neutralization are provided. In certain embodiments, an RF amplifier includes an RF input terminal, an RF output terminal, a gain transistor including a control terminal that receives an RF signal from the RF input terminal, a cascode transistor connected in series with the gain transistor and that provides an amplified RF signal to the RF output terminal, and a neutralization capacitor connected in parallel with the cascode transistor.
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公开(公告)号：US11183984B2
公开(公告)日：2021-11-23
申请号：US16680304
申请日：2019-11-11
Applicant: SKYWORKS SOLUTIONS, INC.
IPC: H03F3/72 , H03F3/68 , H03F1/22 , H03G3/30 , H03F1/32 , H03F1/56 , H03G1/00 , H03G3/00 , H03F3/195 , H03F3/213
Abstract: Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.
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公开(公告)号：US20210143859A1
公开(公告)日：2021-05-13
申请号：US17069745
申请日：2020-10-13
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are methods for amplifying radio-frequency signals using a variable-gain amplifier with a plurality of input nodes. The methods provide a plurality of gain modes with a low gain mode or bypass mode that follows a bypass path through the variable-gain amplifier and a plurality of higher gain modes that take advantage of tailored impedances for particular gain modes. The tailored impedances can be configured to improve linearity of the amplification process in targeted gain modes. The methods can selectively couple the bypass path to a reference potential node in the plurality of higher gain modes and can selectively decouple the input nodes from a degeneration switching block in the bypass mode.
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Patent Agency Ranking
公开(公告)号：US10804951B2
公开(公告)日：2020-10-13
申请号：US16736777
申请日：2020-01-07
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are variable-gain amplifier configurations that include a multi-input gain stage, a cascode buffer, and a bypass block. Degeneration switching blocks can be used for the entire multi-input gain stage or for individual input nodes of the multi-input gain stage. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
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公开(公告)号：US10778150B2
公开(公告)日：2020-09-15
申请号：US16546261
申请日：2019-08-20
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F3/72 , H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03G1/00 , H03G5/28 , H04B1/3827
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers have a first active core with amplification chains for each of a plurality of inputs and a second active core with a single amplification chain to amplify signals received at the plurality of inputs.
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公开(公告)号：US10284160B2
公开(公告)日：2019-05-07
申请号：US15691625
申请日：2017-08-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee
IPC: H03F1/22 , H03G3/30 , H03F3/195 , H03F3/24 , H03G1/00 , H03G3/00 , H03F1/02 , H03F1/56 , H03F3/21 , H03F3/72 , H04B1/16
Abstract: Disclosed herein are signal amplifiers that have an input impedance that varies over different bias currents. The signal amplifier includes a gain stage with a plurality of switchable amplification branches that are each capable of being activated such that one or more of the activated amplification branches provides a targeted adjustment to the input impedance. In addition, disclosed herein are signal amplifiers that have a variable-gain stage configured to provide a plurality of gain levels that result in different input impedance values presented to a respective signal by the variable-gain stage. The variable-gain stage can include a plurality of switchable amplification branches that provide a targeted adjustment to the respective input impedance values. The variable-gain stage can include a plurality of switchable inductive elements that are configured to be activated to provide a targeted adjustment to the respective input impedance values.
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公开(公告)号：US20240048167A1
公开(公告)日：2024-02-08
申请号：US18453205
申请日：2023-08-21
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Stephane Richard Marie Wloczysiak , Thomas Obkircher , Junhyung Lee , Rimal Deep Singh , Bipul Agarwal
CPC classification number: H04B1/1638 , H04J4/00 , H04B1/18 , H04B1/1615 , H04L5/14
Abstract: Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.
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公开(公告)号：US11777549B2
公开(公告)日：2023-10-03
申请号：US17649904
申请日：2022-02-03
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Stephane Richard Marie Wloczysiak , Thomas Obkircher , Junhyung Lee , Rimal Deep Singh , Bipul Agarwal
CPC classification number: H04B1/1638 , H04B1/1615 , H04B1/18 , H04J4/00 , H04L5/14
Abstract: Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.
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