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    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250157959A1

    公开(公告)日：2025-05-15

    申请号：US18662536

    申请日：2024-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon MOON ,  Younghwan SON ,  Sukkang SUNG

    IPC: H01L23/00

    Abstract: A semiconductor device may include a circuit element wire, a lower wire connected to the circuit element wire, a lower interlayer insulation layer on the lower wire, and a first contact pad penetrating the lower interlayer insulation layer. The first contact pad may include a first portion connected to the lower wire, a second portion including a void on the first portion, and a third portion on the second portion. A maximum width between both outer surfaces of the second portion along a horizontal direction may be larger than a width of the third portion along the horizontal direction.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20250107086A1

    公开(公告)日：2025-03-27

    申请号：US18737295

    申请日：2024-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hanbyeol LEE ,  Younghwan SON ,  Sangdon LEE ,  Shinhwan KANG ,  Sukkang SUNG

    IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

    Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.

    SEMICONDUCTOR DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
    7.
    发明公开
    SEMICONDUCTOR DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240315023A1

    公开(公告)日：2024-09-19

    申请号：US18489451

    申请日：2023-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Sukkang SUNG

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L23/5223 ,  H10B41/27

    Abstract: Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    8.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240074203A1

    公开(公告)日：2024-02-29

    申请号：US18357401

    申请日：2023-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  Sukkang SUNG

    IPC: H10B43/50 ,  H10B43/27

    CPC classification number: H10B43/50 ,  H10B43/27

    Abstract: A semiconductor device may include a peripheral circuit structure including cell region and an outside region, a cell structure on the cell region, an outside structure on the outside region, and an insulating layer. The outside structure may include a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure. The insulating layer may be between the dummy stacked structure and the peripheral circuit structure. The dummy stacked structure may include an upper dummy stacked structure on a lower dummy stacked structure. The upper dummy stacked structure may include upper dummy patterns stacked on the lower dummy stacked structure. The lower dummy stacked structure may include lower dummy patterns stacked on the outside region.

    VERTICAL NON-VOLATILE MEMORY DEVICE
    10.
    发明申请
    VERTICAL NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20230109996A1

    公开(公告)日：2023-04-13

    申请号：US17955696

    申请日：2022-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghoon SON ,  Sukkang SUNG ,  Sangdon LEE ,  Euntaek JUNG

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

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