公开(公告)号：US20240191389A1

公开(公告)日：2024-06-13

申请号：US18522817

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeyun PARK ,  Inji LEE

IPC: C30B15/04 ,  C30B15/20 ,  C30B29/06 ,  C30B33/00

CPC classification number: C30B15/04 ,  C30B15/20 ,  C30B29/06 ,  C30B33/00

Abstract: A method of manufacturing a silicon single crystal includes preparing a silicon melt and growing the silicon single crystal based on co-doping boron and phosphorus into the silicon melt. The growing of the silicon single crystal includes controlling, a doping concentration ratio, which is a ratio of an initial concentration of phosphorus to an initial concentration of boron, to be a particular ratio and controlling the initial concentration of boron to be within a range of about 8.0E12 atom/cm3 to about 1.5E13 atom/cm3.

公开(公告)号：US20200243338A1

公开(公告)日：2020-07-30

申请号：US16551930

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-A LEE ,  Yeonsook KIM ,  Inji LEE

IPC: H01L21/225 ,  H01L29/167 ,  H01L21/02 ,  H01L21/322 ,  H01L21/306 ,  H01L21/324

Abstract: An epitaxial wafer and a method of fabricating an epitaxial wafer, the method including providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm3 and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.

公开(公告)号：US20250062228A1

公开(公告)日：2025-02-20

申请号：US18657084

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun PARK ,  Gyuhee PARK ,  Inji LEE ,  Hase NAOKI

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including devices; a lower insulating layer on the substrate; a lower wiring layer on the lower insulating layer and electrically connected to the devices; a first upper insulating layer on the lower insulating layer; an upper contact penetrating through the first upper insulating layer and connected to the lower wiring layer, an upper wiring layer on the first upper insulating layer and connected to the upper contact; and a second upper insulating layer on the first upper insulating layer and covering the upper wiring layer. The upper wiring layer may include an aluminum alloy and 0.01-3 wt % of the aluminum alloy may be at least one dopant among Zn, Ni, V, and Cr. A balance of the aluminum alloy may include Al.