公开(公告)号：US20240105791A1

公开(公告)日：2024-03-28

申请号：US18371869

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin Koo ,  Kyuwan Kim ,  Jonghyeok Kim ,  Hyokyoung Kim ,  Kisoo Park

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.

公开(公告)号：US20230209805A1

公开(公告)日：2023-06-29

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin KOO ,  Kyuwan KIM ,  Kisoo PARK

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US20230186982A1

公开(公告)日：2023-06-15

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung Kang ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H10B10/00 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H10B10/12 ,  H10B10/18 ,  H01L23/5286 ,  H01L27/092

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20220115377A1

公开(公告)日：2022-04-14

申请号：US17331725

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyokyoung KIM ,  Jamin KOO ,  Jonghyeok KIM ,  Daeyoung MOON

IPC: H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.

公开(公告)号：US20210383861A1

公开(公告)日：2021-12-09

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20200005860A1

公开(公告)日：2020-01-02

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20170221554A1

公开(公告)日：2017-08-03

申请号：US15417807

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.