公开(公告)号：US20240105791A1

公开(公告)日：2024-03-28

申请号：US18371869

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin Koo ,  Kyuwan Kim ,  Jonghyeok Kim ,  Hyokyoung Kim ,  Kisoo Park

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.

公开(公告)号：US11729963B2

公开(公告)日：2023-08-15

申请号：US17331725

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyokyoung Kim ,  Jamin Koo ,  Jonghyeok Kim ,  Daeyoung Moon

IPC: H01L27/108 ,  H10B12/00 ,  H01L29/423

CPC classification number: H10B12/30 ,  H01L29/4236

Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.

公开(公告)号：US20250142812A1

公开(公告)日：2025-05-01

申请号：US18896219

申请日：2024-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoun Song ,  Jamin Koo ,  Beomseo Kim ,  Jonghyeok Kim ,  Daeyoung Moon ,  Changwoo Seo ,  Wonseok Yoo ,  Chunhyung Chung

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0