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    INPUT DEVICE ERROR COMPENSATING METHOD AND TERMINAL FOR SUPPORTING THE SAME
    1.
    发明申请
    INPUT DEVICE ERROR COMPENSATING METHOD AND TERMINAL FOR SUPPORTING THE SAME 有权
    输入设备错误补偿方法和终端支持相同

    公开(公告)号：US20140009445A1

    公开(公告)日：2014-01-09

    申请号：US13928831

    申请日：2013-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinman KIM ,  Junhui LEE ,  Byungkyu KIM ,  Sungbin AN

    IPC: G06F3/0354

    CPC classification number: G06F3/03545 ,  G06F1/1694 ,  G06F3/0418 ,  G06F3/046

    Abstract: A method of compensating an error of an input device and an apparatus thereof. An electromagnetic induction pen including a coil for electromagnetic induction spaced apart from a nib of the pen is prepared. A sensor board is provided in the apparatus in which a voltage or current for electromagnetic induction of the electromagnetic induction pen output. A disposition state of the sensor board is determined. The voltage or the current is adjusted and provided to the sensor board formed according to a sensed rotation state of the sensor board or terminal in order to compensate for an error generated due to a distance between the nib and the coil. An error is compensated for by allowing coordinates according to the electromagnetic induction formed on the sensor board and varied with the rotation disposition state of the sensor board to correspond to a position of the nib.

    Abstract translation: 一种补偿输入装置的误差的方法及其装置。 制备包括用于与笔的笔尖间隔开的用于电磁感应的线圈的电磁感应笔。 在用于电磁感应笔的电磁感应的电压或电流输出的装置中设置传感器板。 确定传感器板的布置状态。 电压或电流被调整并提供给根据传感器板或端子的检测到的旋转状态形成的传感器板，以补偿由于笔尖和线圈之间的距离而产生的误差。 通过允许根据传感器基板上形成的电磁感应的坐标并根据传感器板的旋转布置状态而变化的对应于笔尖的位置来补偿误差。

    SEMICONDUCTOR CHIP STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR CHIP STRUCTURE 有权

    公开(公告)号：US20220285208A1

    公开(公告)日：2022-09-08

    申请号：US17453504

    申请日：2021-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangjun PARK ,  Byungkyu KIM ,  Eunji KIM ,  Seungwoo PAEK ,  Sungdong CHO

    IPC: H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

    DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS
    4.
    发明申请
    DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS 有权

    公开(公告)号：US20210407968A1

    公开(公告)日：2021-12-30

    申请号：US17315716

    申请日：2021-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunji KIM ,  Seungwoo PAEK ,  Byungkyu KIM ,  Sangjun PARK ,  Sungdong CHO

    IPC: H01L25/065 ,  H01L23/00 ,  H01L29/423 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L23/498 ,  H01L23/538

    Abstract: A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.

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