公开(公告)号：US12113017B2

公开(公告)日：2024-10-08

申请号：US17651561

申请日：2022-02-17

申请人： QUALCOMM Incorporated

发明人： Thomas Hua-Min Williams ,  Khaja Ahmad Shaik ,  Jeongah Park ,  Rinoj Thomas ,  Harini Siddaiah ,  Raj Kumar

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L29/785

摘要： A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.

公开(公告)号：US11749327B2

公开(公告)日：2023-09-05

申请号：US17459186

申请日：2021-08-27

申请人： QUALCOMM Incorporated

发明人： Khaja Ahmad Shaik ,  Bharani Chava

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/16

CPC分类号： G11C11/005 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/419

摘要： An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.

公开(公告)号：US20220180910A1

公开(公告)日：2022-06-09

申请号：US17459186

申请日：2021-08-27

申请人： QUALCOMM Incorporated

发明人： Khaja Ahmad Shaik ,  Bharani Chava

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/419

摘要： An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.

公开(公告)号：US11176991B1

公开(公告)日：2021-11-16

申请号：US17084779

申请日：2020-10-30

申请人： QUALCOMM Incorporated

发明人： Khaja Ahmad Shaik ,  Bharani Chava ,  Dawuth Shadulkhan Pathan

IPC分类号： G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/404

摘要： Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.