公开(公告)号：US20140252645A1

公开(公告)日：2014-09-11

申请号：US13787476

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Dong Wook Kim ,  Victor A. Chiriac ,  Kyu-Pyung Hwang ,  Changhan Yun ,  Young K. Song

IPC: H01L23/34

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Abstract translation: 一些实施方案提供半导体封装结构，其包括封装衬底，第一封装，耦合到第一封装的插入器和第一组通孔插入件（TVI）。 第一组TVI耦合到插入器和封装衬底。 第一组TVI配置为提供第一包装散热。 在一些实施方案中，半导体封装结构还包括耦合到插入件的散热器。 散热器被配置为从第一包装散发热量。 在一些实施方式中，第一组TVI被进一步配置成在第一封装和封装衬底之间提供电路径。 在一些实施方案中，第一封装通过插入器和第一组TVI电耦合到封装衬底。 在一些实施方案中，第一组TVI包括电介质层和金属层。

公开(公告)号：US20140246753A1

公开(公告)日：2014-09-04

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US09335384B2

公开(公告)日：2016-05-10

申请号：US14037142

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R33/02 ,  G01R29/08

CPC classification number: G01R33/02 ,  G01R29/0814

Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

Abstract translation: 一种用于测试电子设备的近场磁场的方法和装置。 该方法包括使用在第一方向上定向的环形天线来测量磁场。 在测量磁场的同时，将环形天线扫过所需的方位角范围。 一旦第一方向测试完成，环形天线就变成第二定位方向。 然后在第二取向方向上测量磁场，并且扫过第二方向上所需的取向角范围。 该装置提供连接到同轴探针的环形天线，同轴电缆用作中心导体和两个外部导体。 轴安装在环形天线上，并连接到步进电机。 还提供用于移动臂组件的伺服电动机。

公开(公告)号：US20150084653A1

公开(公告)日：2015-03-26

申请号：US14038608

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R27/02 ,  G01R31/28

CPC classification number: G01R27/02

Abstract: A method and apparatus for testing integrated circuit resistors includes applying a variable source current to a resistive device under test (DUT), measuring the resistance of the resistive DUT as a function of the source current, and fitting the measured resistance to parameters of a polynomial parametric equation, wherein the parametric equation comprises a constant resistance at zero current bias plus a second order current coefficient of resistance multiplied by the square of the current.

Abstract translation: 用于测试集成电路电阻的方法和装置包括将可变源电流施加到被测电阻器件（DUT），测量作为源电流的函数的电阻DUT的电阻，并将测得的电阻拟合到多项式的参数 参数方程式，其中参数方程包括零电流偏置处的恒定电阻加上电阻乘以电流平方的二阶电流电流系数。

公开(公告)号：US09837209B2

公开(公告)日：2017-12-05

申请号：US13684072

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Changhan Yun ,  Dong Wook Kim

IPC: H01G4/00 ,  H01G4/30 ,  H01G4/005 ,  H01G4/232 ,  H01G4/224 ,  H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50

CPC classification number: H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19105 ,  Y10T29/417 ,  H01L2924/00

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

公开(公告)号：US09035421B2

公开(公告)日：2015-05-19

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US20140167273A1

公开(公告)日：2014-06-19

申请号：US13719984

申请日：2012-12-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jonghae Kim ,  Chengjie Zuo ,  Changhan Yun ,  Mario Francisco Velez ,  Ravindra V. Shenoy ,  Matthew M. Nowak ,  Francesco Carobolante ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Young K. Song

IPC: H01L23/482 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1517 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer.

Abstract translation: 一个特征涉及集成电路封装的多层封装衬底，其包括具有至少一个电极的分立电路部件（DCC）。 DCC嵌入在绝缘体层内，并且通孔耦合部件电耦合到电极。 通孔耦合部件的第一部分延伸超过电极的第一边缘，并且多个通孔各自具有耦合到第一通路耦合部件的第一端。 多个通孔中的至少第一通孔耦合到延伸超出电极的第一边缘的通孔连接部件的第一部分。 此外，多个通孔各自具有电耦合到第一外部金属层的第二端，并且通孔连接部件的至少第二部分位于第一内部金属层内。

公开(公告)号：US20140132297A1

公开(公告)日：2014-05-15

申请号：US13675673

申请日：2012-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: G01R1/07

CPC classification number: G01R1/07 ,  G01R31/002

Abstract: Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe.

Abstract translation: 描述了用于EMC，EMI和ESD测试的系统和方法。 探针包括沿着探针的轴线延伸的中心导体，探针尖端和与中心导体同轴对准的屏蔽并且被配置为为探针尖端提供电磁屏蔽。 一个或多个致动器可以相对于被测器件改变探头尖端和屏蔽件的相对位置，从而能够控制探头的灵敏度和分辨率。