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公开(公告)号：US10591965B2
公开(公告)日：2020-03-17
申请号：US15411868
申请日：2017-01-20
Applicant: QUALCOMM INCORPORATED
Inventor： Palkesh Jain , Ronald Alton , Jon Anderson , Mehdi Saeidi
IPC: G06F1/20 , G06F9/48 , G06F1/3206
Abstract: Various embodiments of methods and systems context-aware thermal management in a portable computing device (“PCD”) are disclosed. Notably, the environmental context to which a PCD is subjected may have significant impact on the PCD's thermal energy dissipation efficiency. Embodiments of the solution seek to leverage knowledge of a PCD's environmental context to modify or adjust thermal policy parameters applied within a PCD in response to a thermal event within the PCD.
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公开(公告)号：US20170222430A1
公开(公告)日：2017-08-03
申请号：US15012723
申请日：2016-02-01
Applicant: QUALCOMM Incorporated
Inventor： Virendra Bansal , Rahul Gulati , Pranjal Bhuyan , Palkesh Jain
CPC classification number: H02H9/02 , G01R31/025 , G01R31/2853 , H01L23/62
Abstract: An integrated circuit (IC) is disclosed herein for short-resistant output pin circuitry. In an example aspect, an integrated circuit includes a short-resistant pin and an adjacent pin. The integrated circuit also includes a short-resistant pad that is coupled to the short-resistant pin and an adjacent pad that is coupled to the adjacent pin. The integrated circuit further includes short-resistant circuitry that is coupled to the short-resistant pad and the adjacent pad. The short-resistant circuitry is implemented to detect a short-circuit condition between the short-resistant pin and the adjacent pin and to reduce an effect of the short-circuit condition on the short-resistant pin.
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公开(公告)号：US09628089B1
公开(公告)日：2017-04-18
申请号：US15192996
申请日：2016-06-24
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain , Keith Alan Bowman , Virendra Bansal
CPC classification number: H03L7/0802 , H03K5/135 , H03K2005/00019 , H03K2005/00058
Abstract: An adaptive clock distribution (ACD) system with a voltage tracking clock generator (VTCG) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit, to generate a TLD clock by adding a preselected delay to a root clock, and a voltage droop detector for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector selects the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.
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公开(公告)号：US10901020B2
公开(公告)日：2021-01-26
申请号：US16118280
申请日：2018-08-30
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain , Rahul Gulati , Edward Jacob Meisarosh
IPC: G01R29/027 , G06F1/10 , H03K3/037 , H03K7/08
Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.
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公开(公告)号：US10103714B2
公开(公告)日：2018-10-16
申请号：US15058001
申请日：2016-03-01
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain , Manoj Mehrotra , Yuancheng Chris Pan , Shih-Hsin Jason Hu
Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.
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Patent Agency Ranking
公开(公告)号：US20180143862A1
公开(公告)日：2018-05-24
申请号：US15373067
申请日：2016-12-08
Applicant: QUALCOMM INCORPORATED
Inventor： Mehdi Saeidi , Vivek Sahu , Taravat Khadivi , Ryan Coutts , Ronald Alton , Palkesh Jain , Rajat Mittal
CPC classification number: G06F9/5044 , G06F1/206 , G06F9/5094 , Y02D10/22
Abstract: A method includes generating temperature information from a plurality of temperature sensors within a computing device, wherein a first one of the temperature sensors is physically located at a first processing unit of the computing device; processing the temperature information to identify that the first temperature sensor is associated with temperature that is at or above a threshold; and assigning a processing thread to a first core of a plurality of cores of a second processing unit in response to identifying that the first temperature sensor is associated with temperature that is at or above the threshold and based at least in part on a physical distance between the first core and the first temperature sensor.
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公开(公告)号：US09915968B2
公开(公告)日：2018-03-13
申请号：US15133068
申请日：2016-04-19
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain , Virendra Bansal , Manoj Mehrotra , Keith Alan Bowman
Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.
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8.发明申请STOCHASTIC AND TOPOLOGICALLY AWARE ELECTROMIGRATION ANALYSIS METHODOLOGY 审中-公开STOCHASTIC和拓扑学电磁分析方法学公开(公告)号：US20160116527A1
公开(公告)日：2016-04-28
申请号：US14865339
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain
CPC classification number: G06F17/5036 , G01R31/2848
Abstract: A computer-implemented method for analyzing a system comprising a plurality of components is described herein according to certain aspects. The method comprises simulating the system cascading through a plurality of failures until the system fails to meet a system specification, each of the failures corresponding to a failure of one of the components. The method also comprises estimating a time to failure of the system based on a last one of the plurality of failures.
Abstract translation: 本文中根据某些方面描述了用于分析包括多个部件的系统的计算机实现的方法。 该方法包括模拟通过多个故障的系统级联，直到系统不能满足系统规范，每个故障对应于组件之一的故障。 该方法还包括基于多个故障中的最后一个来估计系统故障的时间。
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公开(公告)号：US10389379B2
公开(公告)日：2019-08-20
申请号：US15594322
申请日：2017-05-12
Applicant: QUALCOMM Incorporated
Inventor： Rahul Gulati , Palkesh Jain , Pranjal Bhuyan , Mohammad Reza Kakoee
Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.
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公开(公告)号：US10042405B2
公开(公告)日：2018-08-07
申请号：US14920218
申请日：2015-10-22
Applicant: QUALCOMM Incorporated
Inventor： Palkesh Jain , Manoj Mehrotra
Abstract: Apparatuses and methods to adjust a source voltage based on stored information are provided. The apparatus includes a circuit configured to receive power from a power source through a power distribution network, a storage medium storing data specifying one or more electrical characteristics of the circuit, and a control circuit configured to adjust a source voltage at the power source based on the data stored in the storage medium. The method includes receiving power by a circuit from a power source through a power distribution network, reading data specifying one or more electrical characteristics of the circuit from a storage medium, and adjusting a source voltage at the power source based on the data stored in the storage medium.
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