公开(公告)号：US09263522B2

公开(公告)日：2016-02-16

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US20140225224A1

公开(公告)日：2014-08-14

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US09496254B2

公开(公告)日：2016-11-15

申请号：US14690144

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L23/52 ,  H01L27/06 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20140231957A1

公开(公告)日：2014-08-21

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  PR Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L23/538 ,  H01L27/08

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上互连层的至少一部分的第一电容器板和具有MIM电容层的至少一部分的第二电容器板。

公开(公告)号：US20140138793A1

公开(公告)日：2014-05-22

申请号：US13684059

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL, conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 该方法还包括在MIM电容器的第二板上沉积在绝缘体层上的第二MOL导电层。

公开(公告)号：US20140092523A1

公开(公告)日：2014-04-03

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/005 ,  H01G4/38

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20150221638A1

公开(公告)日：2015-08-06

申请号：US14690144

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20150162404A1

公开(公告)日：2015-06-11

申请号：US14100489

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/22 ,  H01L29/20 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0684 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

Abstract translation: 一种装置包括从第一蚀刻停止层的表面延伸的第一鳍状场效应晶体管（FinFET）器件。 该装置还包括从第二蚀刻停止层的表面延伸的第二FinFET器件。 第一化合物层介于第一蚀刻停止层和第二蚀刻停止层之间。

公开(公告)号：US20140225223A1

公开(公告)日：2014-08-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与传统技术相比，制造金属 - 绝缘体 - 金属（MIM）电容器的方法减少了掩模和处理步骤的数量。 在半导体芯片上构图导电再分布层（RDL）。 MIM电介质层沉积在RDL上。 在MIM电介质层上沉积MIM电容器的第一导电层。 使用MIM导电层掩模对MIM电介质层进行构图。 导电再分配层包括在MIM电容器的第一导电层下延伸的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140197520A1

公开(公告)日：2014-07-17

申请号：US13743434

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  Bin Yang ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L28/24

Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.

Abstract translation: 在特定实施例中，一种方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露光学平坦化层的区域。 至少部分地在该区域内形成电阻层。 该方法还包括去除光学平坦化层的至少第二部分和电阻层的至少第三部分以形成电阻器。