公开(公告)号：US20150109034A1

公开(公告)日：2015-04-23

申请号：US14056861

申请日：2013-10-17

Applicant: QUALCOMM INCORPORATED

Inventor： Narasimhan Vasudevan ,  Zhiqin Chen ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: H03L7/08

CPC classification number: H03L7/0995 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0816

Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

Abstract translation: 这里描述了用于在频率切换期间减少停机时间的延迟架构。 在一个实施例中，可调延迟电路包括被配置为产生偏置电压的锁相环（PLL）或延迟锁定环（DLL）以及串联耦合的多个延迟元件，其中每个延迟元件是 由偏置电压偏置。 可调延迟电路还包括耦合到两个或更多个延迟元件的输出的多路复用器，其中每个输出对应于输入信号的不同延迟，并且其中多路复用器被配置为基于 存储器接口的数据频率。

公开(公告)号：US09490785B1

公开(公告)日：2016-11-08

申请号：US14705733

申请日：2015-05-06

Applicant: QUALCOMM, Incorporated

Inventor： Shraddha Sridhar ,  Jan Christian Diffenderfer ,  Guneet Singh ,  Michael Thomas Fertsch

IPC: H03H11/26 ,  H03K5/06 ,  H03K5/13 ,  H03K5/00

CPC classification number: H03K5/06 ,  H03K3/0315 ,  H03K5/131 ,  H03K2005/00058

Abstract: Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.

Abstract translation: 这里根据本公开的实施例描述了可编程延迟电路。 在一个实施例中，延迟电路包括串联耦合的多个延迟级。 每个延迟级包括在延迟电路的正向路径上的延迟门，其中延迟门配置为根据相应选择信号的逻辑状态在正向路径上传递或阻塞信号。 每个延迟级还包括在延迟电路的返回路径上的复用器，其中多路复用器被配置为在返回路径上传递信号或将前向路径上的信号路由到返回路径，这取决于逻辑状态 各选择信号。 在延迟电路的延迟设置改变期间，延迟门和多路复用器的输出逻辑状态可以保持静态以减少毛刺。

公开(公告)号：US09281810B2

公开(公告)日：2016-03-08

申请号：US14276644

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Guneet Singh ,  Hayden Clavie Cranford, Jr. ,  Michael Thomas Fertsch

IPC: H03K3/00 ,  H03K5/01

CPC classification number: H03K5/01 ,  H03K19/018514 ,  H03K19/09432

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract translation: 公开了一种包括时钟电路，控制电路和电流模式逻辑（CML）电路的装置。 时钟电路提供第一差分时钟信号，并且控制电路至少部分地基于第一差分时钟信号的频率产生控制信号。 CML电路至少部分地基于第一差分时钟信号产生第二差分时钟信号。 至少部分地基于控制信号，CML电路以多个不同的频率模式中的一种工作，并且包括响应于控制信号的多个可变电阻器。

公开(公告)号：US20150108842A1

公开(公告)日：2015-04-23

申请号：US14056851

申请日：2013-10-17

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Narasimhan Vasudevan ,  Michael Thomas Fertsch

IPC: H02J1/00

CPC classification number: H02J1/108 ,  H02J1/10 ,  Y10T307/549

Abstract: Techniques for reducing cross-supply current are described herein. In one embodiment, a power circuit comprises a bypass switch coupled between a first power supply and an internal power supply, and a voltage regulator coupled between a second power supply and the internal power supply. The power circuit also comprises a shut-off circuit configured to detect the first power supply powering up before the second power supply during a power-up sequence, to shut off the bypass switch upon detecting the first power supply powering up before the second power supply, to detect the second power supply powering up during the power-up sequence, and to release control of the bypass switch to a controller upon detecting the second power supply powering up.

Abstract translation: 本文描述了用于降低交叉电源电流的技术。 在一个实施例中，电源电路包括耦合在第一电源和内部电源之间的旁路开关以及耦合在第二电源和内部电源之间的电压调节器。 电源电路还包括关断电路，被配置为在上电序列期间检测在第二电源之前供电的第一电源，以在检测到在第二电源之前检测到第一电源供电时关闭旁路开关 检测在上电序列期间上电的第二电源，并且在检测到第二电源供电时，将旁路开关的控制释放到控制器。

公开(公告)号：US20150106538A1

公开(公告)日：2015-04-16

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US20160329884A1

公开(公告)日：2016-11-10

申请号：US14705733

申请日：2015-05-06

Applicant: QUALCOMM, Incorporated

Inventor： Shraddha Sridhar ,  Jan Christian Diffenderfer ,  Guneet Singh ,  Michael Thomas Fertsch

IPC: H03K5/06 ,  H03K5/13

CPC classification number: H03K5/06 ,  H03K3/0315 ,  H03K5/131 ,  H03K2005/00058

Abstract: Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.

Abstract translation: 这里根据本公开的实施例描述了可编程延迟电路。 在一个实施例中，延迟电路包括串联耦合的多个延迟级。 每个延迟级包括在延迟电路的正向路径上的延迟门，其中延迟门配置为根据相应选择信号的逻辑状态在正向路径上传递或阻塞信号。 每个延迟级还包括在延迟电路的返回路径上的复用器，其中多路复用器被配置为在返回路径上传递信号或将前向路径上的信号路由到返回路径，这取决于逻辑状态 各选择信号。 在延迟电路的延迟设置改变期间，延迟门和多路复用器的输出逻辑状态可以保持静态以减少毛刺。

公开(公告)号：US09305632B2

公开(公告)日：2016-04-05

申请号：US13901511

申请日：2013-05-23

Applicant: QUALCOMM Incorporated

Inventor： Zeeshan Shafaq Syed ,  Nan Chen ,  Yong Xu ,  Michael Thomas Fertsch ,  Boris Dimitrov Andreev ,  Zhiqin Chen ,  Chang Ki Kwon

IPC: G06F1/32 ,  G11C11/4074

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract translation: 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。

公开(公告)号：US09213487B2

公开(公告)日：2015-12-15

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US20150333743A1

公开(公告)日：2015-11-19

申请号：US14276644

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Guneet Singh ,  Hayden Clavie Cranford, JR. ,  Michael Thomas Fertsch

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03K19/018514 ,  H03K19/09432

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract translation: 公开了一种包括时钟电路，控制电路和电流模式逻辑（CML）电路的装置。 时钟电路提供第一差分时钟信号，并且控制电路至少部分地基于第一差分时钟信号的频率产生控制信号。 CML电路至少部分地基于第一差分时钟信号产生第二差分时钟信号。 至少部分地基于控制信号，CML电路以多个不同的频率模式中的一种工作，并且包括响应于控制信号的多个可变电阻器。