公开(公告)号：US11120863B2

公开(公告)日：2021-09-14

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Vaishnav Srinivas ,  Mahalingam Nagarajan ,  Yong Xu

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/409 ,  G06F13/42

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US11662765B1

公开(公告)日：2023-05-30

申请号：US17574722

申请日：2022-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Christophe Avoinne ,  Xavier Loic Leloup ,  Michael David Jager

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

公开(公告)号：US11551730B2

公开(公告)日：2023-01-10

申请号：US17158485

申请日：2021-01-26

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Joon Young Park ,  Mahalingam Nagarajan

IPC: G11C5/02 ,  G11C5/14 ,  H03K7/02

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

公开(公告)号：US20220238142A1

公开(公告)日：2022-07-28

申请号：US17158485

申请日：2021-01-26

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Joon Young Park ,  Mahalingam Nagarajan

IPC: G11C5/14 ,  H03K7/02

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

公开(公告)号：US11823762B2

公开(公告)日：2023-11-21

申请号：US18150155

申请日：2023-01-04

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Joon Young Park ,  Mahalingam Nagarajan

IPC: G11C5/02 ,  G11C5/14 ,  H03K7/02

CPC classification number: G11C5/147 ,  H03K7/02

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

公开(公告)号：US11493949B2

公开(公告)日：2022-11-08

申请号：US16832855

申请日：2020-03-27

Applicant: Qualcomm Incorporated

Inventor： Farrukh Aquil ,  Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Yong Xu

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/16

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.