公开(公告)号：US11372717B2

公开(公告)日：2022-06-28

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US11662765B1

公开(公告)日：2023-05-30

申请号：US17574722

申请日：2022-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Christophe Avoinne ,  Xavier Loic Leloup ,  Michael David Jager

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

公开(公告)号：US11295803B2

公开(公告)日：2022-04-05

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.