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公开(公告)号：US11095301B1
公开(公告)日：2021-08-17
申请号：US16945090
申请日：2020-07-31
Applicant: QUALCOMM Incorporated
Inventor： Yongjian Tang , Chieh-Yu Hsieh , Lei Sun , Anand Meruva , Seyed Arash Mirhaj , Yuhua Guo , Dinesh Jagannath Alladi
Abstract: Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.
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公开(公告)号：US10594308B1
公开(公告)日：2020-03-17
申请号：US16236721
申请日：2018-12-31
Applicant: QUALCOMM Incorporated
Inventor： Lei Sun , Ganesh Kiran , Seyed Arash Mirhaj , Dinesh Jagannath Alladi
Abstract: Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.
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公开(公告)号：US09300316B2
公开(公告)日：2016-03-29
申请号：US14616464
申请日：2015-02-06
Applicant: QUALCOMM Incorporated
Inventor： Dinesh Jagannath Alladi , Sean Baker , Balasubramanian Sivakumar , Wei Huang , Dan Yuan
CPC classification number: H03M1/1245 , H03M1/0682 , H03M1/38 , H03M1/403 , H03M1/468 , H03M1/66
Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.
Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。
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公开(公告)号：US20150249463A1
公开(公告)日：2015-09-03
申请号：US14616464
申请日：2015-02-06
Applicant: QUALCOMM Incorporated
Inventor： Dinesh Jagannath Alladi , Sean Baker , Balasubramanian Sivakumar , Wei Huang , Dan Yuan
CPC classification number: H03M1/1245 , H03M1/0682 , H03M1/38 , H03M1/403 , H03M1/468 , H03M1/66
Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.
Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。
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公开(公告)号：US11962317B2
公开(公告)日：2024-04-16
申请号：US17804779
申请日：2022-05-31
Applicant: QUALCOMM Incorporated
Inventor： Behnam Sedighi , Shi Bu , Elias Dagher , Dinesh Jagannath Alladi
IPC: H03M1/08
CPC classification number: H03M1/0854
Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.
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Patent Agency Ranking
公开(公告)号：US20220368299A1
公开(公告)日：2022-11-17
申请号：US17320077
申请日：2021-05-13
Applicant: Qualcomm Incorporated
Inventor： Kentaro Yamamoto , Aram Akhavan , Ganesh Kiran , Lei Sun , Elias Dagher , Dinesh Jagannath Alladi
Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.
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公开(公告)号：US11294413B2
公开(公告)日：2022-04-05
申请号：US16835494
申请日：2020-03-31
Applicant: QUALCOMM Incorporated
Inventor： Balasubramanian Sivakumar , Dinesh Jagannath Alladi , Kentaro Yamamoto , Sean Baker , Liang Zhao
Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.
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公开(公告)号：US09998138B1
公开(公告)日：2018-06-12
申请号：US15711021
申请日：2017-09-21
Applicant: QUALCOMM Incorporated
Inventor： Yan Wang , Chieh-Yu Hsieh , Ji Ma , Seyed Arash Mirhaj , Dinesh Jagannath Alladi
CPC classification number: H03M1/462 , H03M1/12 , H03M1/1215 , H03M1/38 , H03M1/46 , H03M1/80 , H03M1/804
Abstract: Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.
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公开(公告)号：US20160246317A1
公开(公告)日：2016-08-25
申请号：US14630481
申请日：2015-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Dinesh Jagannath Alladi , Dan Yuan
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: In one embodiment, a method for generating a reference comprises generating a current that is approximately temperature independent over a temperature range based on an emitter-base voltage of a first bipolar junction transistor (BJT), and generating a first proportional to absolute temperature (PTAT) current based on the emitter-base voltage of the first BJT.
Abstract translation: 在一个实施例中，用于产生参考的方法包括基于第一双极结型晶体管（BJT）的发射极 - 基极电压产生在温度范围上近似温度独立的电流，并产生与绝对温度成比例的第一（PTAT ）电流基于第一BJT的发射极 - 基极电压。
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公开(公告)号：US11870404B2
公开(公告)日：2024-01-09
申请号：US17320077
申请日：2021-05-13
Applicant: Qualcomm Incorporated
Inventor： Kentaro Yamamoto , Aram Akhavan , Ganesh Kiran , Lei Sun , Elias Dagher , Dinesh Jagannath Alladi
CPC classification number: H03G3/3036 , H03F3/19 , H03F3/21 , H03M1/124 , H03F2200/453
Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.
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