公开(公告)号：US20160246317A1

公开(公告)日：2016-08-25

申请号：US14630481

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Dinesh Jagannath Alladi ,  Dan Yuan

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: In one embodiment, a method for generating a reference comprises generating a current that is approximately temperature independent over a temperature range based on an emitter-base voltage of a first bipolar junction transistor (BJT), and generating a first proportional to absolute temperature (PTAT) current based on the emitter-base voltage of the first BJT.

Abstract translation: 在一个实施例中，用于产生参考的方法包括基于第一双极结型晶体管（BJT）的发射极 - 基极电压产生在温度范围上近似温度独立的电流，并产生与绝对温度成比例的第一（PTAT ）电流基于第一BJT的发射极 - 基极电压。

公开(公告)号：US11196434B1

公开(公告)日：2021-12-07

申请号：US17062193

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Lei Sun ,  Honghao Ji ,  Dan Yuan

IPC: H03M1/38 ,  H03M1/06

Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

公开(公告)号：US09300316B2

公开(公告)日：2016-03-29

申请号：US14616464

申请日：2015-02-06

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Jagannath Alladi ,  Sean Baker ,  Balasubramanian Sivakumar ,  Wei Huang ,  Dan Yuan

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/66 ,  H03M1/06 ,  H03M1/40 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/0682 ,  H03M1/38 ,  H03M1/403 ,  H03M1/468 ,  H03M1/66

Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.

Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。

公开(公告)号：US20150249463A1

公开(公告)日：2015-09-03

申请号：US14616464

申请日：2015-02-06

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Jagannath Alladi ,  Sean Baker ,  Balasubramanian Sivakumar ,  Wei Huang ,  Dan Yuan

IPC: H03M1/12 ,  H03M1/66 ,  H03M1/38

CPC classification number: H03M1/1245 ,  H03M1/0682 ,  H03M1/38 ,  H03M1/403 ,  H03M1/468 ,  H03M1/66

Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.

Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。