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公开(公告)号：US11294413B2
公开(公告)日：2022-04-05
申请号：US16835494
申请日：2020-03-31
Applicant: QUALCOMM Incorporated
Inventor： Balasubramanian Sivakumar , Dinesh Jagannath Alladi , Kentaro Yamamoto , Sean Baker , Liang Zhao
Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.
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Patent Agency Ranking
2.发明授权公开(公告)号：US10312927B1
公开(公告)日：2019-06-04
申请号：US15935988
申请日：2018-03-26
Applicant: QUALCOMM Incorporated
Inventor： Seyed Arash Mirhaj , Elias Dagher , Yongjian Tang , Dinesh Alladi , Masoud Ensafdaran , Lei Sun , Anand Meruva , Yuhua Guo , Balasubramanian Sivakumar
Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.
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公开(公告)号：US10439627B2
公开(公告)日：2019-10-08
申请号：US16010117
申请日：2018-06-15
Applicant: Qualcomm Incorporated
Inventor： Sean Baker , Dinesh Jagannath Alladi , Balasubramanian Sivakumar , Kentaro Yamamoto
IPC: H03M1/06 , H03M1/00 , H04B1/3827
Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.
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公开(公告)号：US20190190529A1
公开(公告)日：2019-06-20
申请号：US16010117
申请日：2018-06-15
Applicant: Qualcomm Incorporated
Inventor： Sean Baker , Dinesh Jagannath Alladi , Balasubramanian Sivakumar , Kentaro Yamamoto
CPC classification number: H03M1/0629 , H03M1/002 , H03M1/468 , H04B1/3827
Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.
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公开(公告)号：US09300316B2
公开(公告)日：2016-03-29
申请号：US14616464
申请日：2015-02-06
Applicant: QUALCOMM Incorporated
Inventor： Dinesh Jagannath Alladi , Sean Baker , Balasubramanian Sivakumar , Wei Huang , Dan Yuan
CPC classification number: H03M1/1245 , H03M1/0682 , H03M1/38 , H03M1/403 , H03M1/468 , H03M1/66
Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.
Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。
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公开(公告)号：US20150249463A1
公开(公告)日：2015-09-03
申请号：US14616464
申请日：2015-02-06
Applicant: QUALCOMM Incorporated
Inventor： Dinesh Jagannath Alladi , Sean Baker , Balasubramanian Sivakumar , Wei Huang , Dan Yuan
CPC classification number: H03M1/1245 , H03M1/0682 , H03M1/38 , H03M1/403 , H03M1/468 , H03M1/66
Abstract: In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.
Abstract translation: 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。
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