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    POWER SAVING DURING A CONNECTION DETECTION
    1.
    发明申请
    POWER SAVING DURING A CONNECTION DETECTION 审中-公开
    在连接检测期间节电

    公开(公告)号：US20160378166A1

    公开(公告)日：2016-12-29

    申请号：US15260355

    申请日：2016-09-09

    Applicant: QUALCOMM Incorporated

    Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Quoc Vuong ,  Xiaohua Kong

    IPC: G06F1/32 ,  G06F11/30 ,  G06F11/22 ,  G06F13/40

    Abstract: An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.

    Abstract translation: 电子设备包括接收机感测电路，其被配置为响应于经由连接器检测到与设备的连接而产生检测信号。 电子设备还包括耦合到热插拔检测（HPD）接口的控制器。 控制器被配置为基于从接收机感测电路接收的检测信号来启用直流（DC）电压源。

    Power saving during a connection detection
    4.
    发明授权
    Power saving during a connection detection 有权
    连接检测期间省电

    公开(公告)号：US09465424B2

    公开(公告)日：2016-10-11

    申请号：US14167000

    申请日：2014-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Q. Vuong ,  Xiaohua Kong

    IPC: G06F1/26 ,  G06F1/16 ,  G06F1/32

    CPC classification number: G06F1/3278 ,  G06F1/1632 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3281 ,  G06F11/2289 ,  G06F11/3041 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/3089 ,  G06F13/4022 ,  G06F13/4081 ,  Y02D10/151 ,  Y10T307/76

    Abstract: In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal.

    Abstract translation: 在特定实施例中，电子设备包括耦合到DC接口的直流（DC）电压源。 电子设备包括接收器感测电路，其被配置为经由连接器检测电子设备到宿设备的连接，而不消耗来自DC电压源的电力。 电子设备还包括耦合到热插拔检测（HPD）接口的控制器。 控制器被配置为从接收器感测电路接收检测信号，选择性地控制开关以基于检测信号启用和禁用DC电压源，在启用直流电压源之后检测HPD接口处的HPD信号，并禁用 接收机感测电路响应于检测到HPD信号。

    High speed data testing without high speed bit clock
    5.
    发明授权
    High speed data testing without high speed bit clock 有权
    无高速位时钟的高速数据测试

    公开(公告)号：US09037437B2

    公开(公告)日：2015-05-19

    申请号：US14105213

    申请日：2013-12-13

    Applicant: QUALCOMM Incorporated

    Inventor： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

    IPC: G06F11/30 ,  G01R31/3177 ,  G09G5/00 ,  G06F1/04

    CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    6.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 有权
    高速数据测试无高速位时钟

    公开(公告)号：US20140101507A1

    公开(公告)日：2014-04-10

    申请号：US14105213

    申请日：2013-12-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

    IPC: G01R31/3177 ,  G06F1/04

    CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    Low-power high-speed CMOS clock generation circuit
    7.
    发明授权
    Low-power high-speed CMOS clock generation circuit 有权

    公开(公告)号：US11626865B1

    公开(公告)日：2023-04-11

    申请号：US17481666

    申请日：2021-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jianwen Ye ,  Bo Sun ,  Cheng Zhong

    IPC: H03K5/01 ,  H03K19/20 ,  H03L7/081 ,  H03K5/00 ,  H04B1/40 ,  H04L12/40

    Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

    POWER SAVING DURING A CONNECTION DETECTION
    9.
    发明申请
    POWER SAVING DURING A CONNECTION DETECTION 有权
    在连接检测期间节电

    公开(公告)号：US20140149756A1

    公开(公告)日：2014-05-29

    申请号：US14167000

    申请日：2014-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Q. Vuong ,  Xiaohua Kong

    IPC: G06F1/26 ,  G06F1/16

    CPC classification number: G06F1/3278 ,  G06F1/1632 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3281 ,  G06F11/2289 ,  G06F11/3041 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/3089 ,  G06F13/4022 ,  G06F13/4081 ,  Y02D10/151 ,  Y10T307/76

    Abstract: In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal.

    Abstract translation: 在特定实施例中，电子设备包括耦合到DC接口的直流（DC）电压源。 电子设备包括接收器感测电路，其被配置为经由连接器检测电子设备到宿设备的连接，而不消耗来自DC电压源的电力。 电子设备还包括耦合到热插拔检测（HPD）接口的控制器。 控制器被配置为从接收器感测电路接收检测信号，选择性地控制开关以基于检测信号启用和禁用DC电压源，在启用直流电压源之后检测HPD接口处的HPD信号，并禁用 接收机感测电路响应于检测到HPD信号。

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