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公开(公告)号：US20210359653A1
公开(公告)日：2021-11-18
申请号：US17227583
申请日：2021-04-12
Applicant: MEDIATEK INC.
Inventor： Fong-Wen LEE , Wen-Chieh WANG , Yu-Hsin LIN
Abstract: A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.
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公开(公告)号：US20210328554A1
公开(公告)日：2021-10-21
申请号：US17184805
申请日：2021-02-25
Applicant: MEDIATEK INC.
Inventor： Fong-Wen LEE , Yu-Hsin LIN
Abstract: A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.
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3.发明申请公开(公告)号：US20150180420A1
公开(公告)日：2015-06-25
申请号：US14643240
申请日：2015-03-10
Applicant: MediaTek Inc.
Inventor： Chen-Yen HO , Chi-Lun LO , Hung-Chieh TSAI , Yu-Hsin LIN
CPC classification number: H03F1/0205 , H03F3/265 , H03F3/30 , H03F3/3023 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/18 , H03F2203/30021 , H03F2203/30033 , H03F2203/45022 , H03F2203/45134 , H03F2203/45138 , H03M3/39 , H03M3/50
Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level. The AC-coupled push-pull output stage further includes a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier. Further, the AC-coupled push-pull output stage includes an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor.
Abstract translation: 放大器包括前端增益级和AC耦合推挽输出级。 AC耦合推挽输出级包括具有源极，漏极和栅极的第一晶体管，其中第一晶体管的源极耦合到第一电压电平。 AC耦合推挽输出级还包括具有源极，漏极和栅极的第二晶体管，其中第二晶体管的源极耦合到第二电压电平，第二晶体管的栅极耦合到 前端增益级，第二晶体管的漏极耦合到第一晶体管的漏极，以形成放大器的输出端。 此外，AC耦合推挽输出级包括AC耦合电容器，其是耦合在前端增益级与第一晶体管的栅极之间的无源双端电气部件。
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4.发明申请公开(公告)号：US20140103999A1
公开(公告)日：2014-04-17
申请号：US14134944
申请日：2013-12-19
Applicant: MediaTek Inc.
Inventor： Chen-Yen HO , Chi-Lun LO , Hung-Chieh TSAI , Yu-Hsin LIN
CPC classification number: H03F1/0205 , H03F3/265 , H03F3/30 , H03F3/3023 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/18 , H03F2203/30021 , H03F2203/30033 , H03F2203/45022 , H03F2203/45134 , H03F2203/45138 , H03M3/39 , H03M3/50
Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor;and a resistance component, coupling the gate of the first transistor to a bias voltage level.
Abstract translation: 放大器包括前端增益级和AC耦合推挽输出级。 AC耦合推挽输出级包括具有源极，漏极和栅极的第一晶体管，其中第一晶体管的源极耦合到第一电压电平; 具有源极，漏极和栅极的第二晶体管，其中所述第二晶体管的源极耦合到第二电压电平，所述第二晶体管的栅极耦合到所述前端增益级，并且所述漏极 第二晶体管耦合到第一晶体管的漏极，以形成放大器的输出端; AC耦合电容器，其是耦合在前端增益级与第一晶体管的栅极之间的无源双端电气元件; 以及电阻分量，将第一晶体管的栅极耦合到偏置电压电平。
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公开(公告)号：US20220255516A1
公开(公告)日：2022-08-11
申请号：US17542675
申请日：2021-12-06
Applicant: MEDIATEK INC.
Inventor： Yu-Hsin LIN , Fong-Wen LEE , Wen-Chieh WANG
IPC: H03F3/45
Abstract: An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170070216A1
公开(公告)日：2017-03-09
申请号：US15338628
申请日：2016-10-31
Applicant: MediaTek Inc.
Inventor： Yu-Hsin LIN , Tze-Chien WANG
IPC: H03K5/02
CPC classification number: H03K5/02 , H03F1/26 , H03F3/26 , H03F3/45475 , H03F3/45928 , H03F2200/06 , H03F2200/261 , H03F2200/78 , H03F2203/45138 , H03F2203/45594
Abstract: A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.
Abstract translation: 提供了用于将输入信号转换成一对差分信号的单端到差分转换电路。 放大器包括反相输入端子，用于接收参考信号的非反相输入端子和输出端子。 第一电阻器耦合在反相输入端子和放大器的输出端子之间。 第二电阻耦合到放大器的反相输入端。 第三电阻耦合到放大器的输出端。 电阻串耦合在放大器的输出端和第二电阻之间，并包括串联连接的第四电阻和第五电阻。 一对差分信号的信号经由第三电阻器提供，并且该对差分信号的另一个信号通过电阻串提供。
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公开(公告)号：US20130214951A1
公开(公告)日：2013-08-22
申请号：US13760379
申请日：2013-02-06
Applicant: MediaTek Inc.
Inventor： Chen-Yen HO , Chi-Lun LO , Hung-Chieh TSAI , Yu-Hsin LIN
IPC: H03M3/00
Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator includes a multi-stage loop filter, a quantizer, and a digital-to-analog converter. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. Each stage of the multi-stage loop filter includes a feedback network. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. The digital-to-analog converter receives the digital output signal and converts the digital output signal to a compensation signal. The digital-to-analog converter provides the compensation signal to a plurality of internal nodes in the feedback network of the last stage of the multi-stage loop filter.
Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器，量化器和数模转换器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 多级环路滤波器的每一级都包括反馈网络。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 数模转换器接收数字输出信号并将数字输出信号转换成补偿信号。 数模转换器向多级环路滤波器的最后级的反馈网络中的多个内部节点提供补偿信号。
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公开(公告)号：US20130207718A1
公开(公告)日：2013-08-15
申请号：US13758028
申请日：2013-02-04
Applicant: MEDIATEK INC.
Inventor： Yu-Hsin LIN , Hung-Chieh TSAI , Chi-Lun LO , Chen-Yen HO
IPC: H03H11/12
CPC classification number: H03H11/1204 , H03H11/1252 , H03H11/126
Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.
Abstract translation: 提供了一个过滤器。 滤波器接收输入信号，并根据输入信号产生输出信号。 滤波器包括输入网络，高通网络和操作电路。 第一输入网络为输入信号提供第一正常路径以产生第一正常信号。 第一高通网络为输入信号提供第一高通路径以产生第一高通信号。 该操作电路具有第一和第二输入端。 第二输入端子的极性与第一输入端子的极性相反。 操作电路由第一输入端接收第一正常信号和由第二输入端接收第一高通信号，使得对第一正常信号和第一高通滤波器执行减法运算以完成低通 用于产生输出信号的滤波操作。
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公开(公告)号：US20140159930A1
公开(公告)日：2014-06-12
申请号：US14097451
申请日：2013-12-05
Applicant: MediaTek Inc.
Inventor： Chen-Yen HO , Hung-Chieh TSAI , Yu-Hsin LIN
IPC: H03M3/00
Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.
Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。
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公开(公告)号：US20240154870A1
公开(公告)日：2024-05-09
申请号：US18496901
申请日：2023-10-29
Applicant: MEDIATEK INC.
Inventor： YUAN-CHIEH Lin , Yu-Hsin LIN
IPC: H04L41/0893 , H04L67/147 , H04W28/18
CPC classification number: H04L41/0893 , H04L67/147 , H04W28/18
Abstract: Methods and apparatus are provided for the UE handling RSD parameters for MA preferences when the UE is in S1 mode. In one novel aspect, the MA PDU preference is applicable for a UE attached to EPS if the UE supports MA PDU session and procedures for PDN connection establishment and a mapped EPS parameter description of an MA preference type of the selected RSD indicates the MA preference. In one embodiment, the selected RSD indicates MA preference when the EPS parameter description of an MA preference type indicates that the PDN connection should be established as a user-plane resource of a multi-access PDU session if the UE supports MA PDU session and procedures for PDN connection establishment. In one embodiment, the PDN connection is established via a PDN connectivity procedure in an EPS or an EPC.
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