公开(公告)号：US20220255516A1

公开(公告)日：2022-08-11

申请号：US17542675

申请日：2021-12-06

Applicant: MEDIATEK INC.

Inventor： Yu-Hsin LIN ,  Fong-Wen LEE ,  Wen-Chieh WANG

IPC: H03F3/45

Abstract: An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.

公开(公告)号：US20190089366A1

公开(公告)日：2019-03-21

申请号：US16000350

申请日：2018-06-05

Applicant: MEDIATEK INC.

Inventor： Fong-Wen LEE

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/12

Abstract: An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital representation, and comprises an input buffer and an analog-to-digital conversion module. The input buffer outputs a positive differential signal and a negative differential signal based on the single-ended analog input. The analog-to-digital conversion module receives the positive differential signal and the negative differential signal to generate the digital representation. The input buffer further transmits a noise compensation signal to the analog-to-digital conversion module. The noise compensation signal contains noise information about noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal. The analog-to-digital conversion module uses the noise compensation signal to compensate for the noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal.

公开(公告)号：US20210359653A1

公开(公告)日：2021-11-18

申请号：US17227583

申请日：2021-04-12

Applicant: MEDIATEK INC.

Inventor： Fong-Wen LEE ,  Wen-Chieh WANG ,  Yu-Hsin LIN

IPC: H03F3/217 ,  H03K19/21

Abstract: A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

公开(公告)号：US20210328554A1

公开(公告)日：2021-10-21

申请号：US17184805

申请日：2021-02-25

Applicant: MEDIATEK INC.

Inventor： Fong-Wen LEE ,  Yu-Hsin LIN

IPC: H03F1/32 ,  H03F3/45

Abstract: A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

公开(公告)号：US20210265959A1

公开(公告)日：2021-08-26

申请号：US17132166

申请日：2020-12-23

Applicant: MEDIATEK INC.

Inventor： Fong-Wen LEE ,  Kuan-Ta CHEN

IPC: H03F3/217 ,  H03F1/34 ,  H03F1/26

Abstract: A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.