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公开(公告)号：US20180069577A1
公开(公告)日：2018-03-08
申请号：US15443541
申请日：2017-02-27
CPC分类号： H04B1/1027 , H04B1/04 , H04L7/0016 , H04L27/06
摘要： A receiver has a receiving unit to receive a radio signal, a signal detector to detect a reception signal in each of a plurality of set periods shifted in time to be overlapped in a partial period, and a demodulating unit to perform demodulation processing based on the reception signal. The signal detector has a smoothing unit to smooth the output signal of the receiving unit in each of the plurality of set periods, a comparing unit to output a signal obtained by comparing a level of the smoothed signal, with a threshold value, and an initializing unit to initialize the signal smoothed by the smoothing processing unit, every time the comparing unit compares the smoothed signal with the threshold value, and the demodulating unit performs the demodulation processing based on the smoothed signal determined to be the threshold value or more by the comparing unit.
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公开(公告)号：US20170373709A1
公开(公告)日：2017-12-28
申请号：US15462232
申请日：2017-03-17
发明人： Satoshi KONDO , Akihide SAI , Tuan Thanh TA , Hidenori OKUNI , Masanori FURUTA , Tetsuro ITAKURA
CPC分类号： H04B1/16 , G04F10/005 , H03G3/3042 , H03G3/3052 , H03L7/085 , H03L7/0891 , H03L7/091 , H03L7/095 , H03L7/0991 , H03L2207/50
摘要： A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.
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公开(公告)号：US20160182066A1
公开(公告)日：2016-06-23
申请号：US14974922
申请日：2015-12-18
发明人： Tuan Thanh TA , Hidenori OKUNI , Akihide SAI , Masanori FURUTA
IPC分类号： H03L7/099
CPC分类号： H03L7/18 , H03D3/007 , H03L7/093 , H04L27/0014 , H04L27/2657 , H04L2027/0028 , H04L2027/0053 , H04L2027/0065
摘要： According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second time shifter. The peak time detector detects, from the digital signal, a first time at which the digital signal exhibits one of a maximal value and a minimal value. The first time shifter adds or subtracts a first natural number multiple of the predetermined period to or from the first time. The zero-crossing time detector detects, from the digital signal, a second time at which the digital signal exhibits one of a positive zero-crossing and a negative zero-crossing. The second time shifter adds or subtracts the first natural number multiple of the predetermined period to or from the second time.
摘要翻译： 根据实施例，自动频率控制电路包括峰值时间检测器，第一时间移位器，过零时间检测器和第二时间移位器。 峰值时间检测器从数字信号中检测数字信号呈现最大值和最小值之一的第一次。 第一时间移位器向第一次或从第一次添加或减去预定周期的第一自然数倍数。 过零时间检测器从数字信号检测数字信号呈现正过零和负过零之一的第二时间。 第二时间移位器向第二次添加或从第二次减去预定时段的第一自然数倍数。
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公开(公告)号：US20150349753A1
公开(公告)日：2015-12-03
申请号：US14720640
申请日：2015-05-22
IPC分类号： H03K3/012
摘要： An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result.
摘要翻译： 根据一个实施例的积分电路包括第一电容元件，电容电路，比较电路，存储器电路和操作电路。 第一电容元件接收电流信号。 电容电路包括第一开关和第二电容元件，并且并联连接到第一电容元件。 第二电容元件经由第一开关接收电流信号。 比较电路将第一电容元件的电压与参考电压进行比较，以获得比较结果。 存储电路存储比较结果，并且基于比较结果来打开或关闭第一开关。 操作电路基于由第一电容元件获得的积分值与第二电容元件之间的差值和基于比较结果的值输出残差信号。
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公开(公告)号：US20150263679A1
公开(公告)日：2015-09-17
申请号：US14621133
申请日：2015-02-12
发明人： Tetsuro ITAKURA , Masanori FURUTA
CPC分类号： H03F3/3028 , H03F1/308 , H03F2200/291 , H03F2203/30084 , H03F2203/30117
摘要： An inverting amplifier according to a first embodiment includes an inverter circuit, a first voltage generating circuit, and a second voltage generating circuit. The inverter circuit has an input terminal, an output terminal, a first first-conductivity transistor, and a first second-conductivity transistor. The first (second) voltage generating circuit has a first (second) current source, a second first (second)-conductivity transistor, and a third first (second)-conductivity transistor. The first (second) current source supplies a predetermined current. The second first (second)-conductivity transistor has a control terminal with a predetermined bias voltage applied, and two ends connected to the other end of the first first (second)-conductivity transistor and the first (second) current source, respectively. The third first (second)-conductivity transistor has a control terminal connected to the other end of the second first (second)-conductivity transistor, and one end connected to one end of the second first (second)-conductivity transistor.
摘要翻译： 根据第一实施例的反相放大器包括逆变器电路，第一电压产生电路和第二电压产生电路。 逆变器电路具有输入端子，输出端子，第一第一导电晶体管和第一第二导电晶体管。 第一（第二）电压产生电路具有第一（第二）电流源，第二第一（第二） - 导电晶体管和第三第一（第二） - 导电晶体管。 第一（第二）电流源提供预定电流。 第二第一（第二） - 导体晶体管具有施加预定偏置电压的控制端子，并且两端分别连接到第一第一（第二） - 导体晶体管和第一（第二）电流源的另一端。 第三第一（第二） - 导体晶体管具有连接到第二第一（第二） - 导体晶体管的另一端的控制端，并且一端连接到第二第一（第二） - 导体晶体管的一端。
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6.发明申请公开(公告)号：US20150160677A1
公开(公告)日：2015-06-11
申请号：US14561705
申请日：2014-12-05
IPC分类号： G05F3/02
摘要： There is provided a single to differential conversion circuit including: a divider circuit, first and second bias current generators, first and second output terminals and a current generating circuit. The divider circuit receives an input current including a DC component and an AC component and divides the input current to generate a first current and a second current. The first bias current generator generates a first bias current. The first output terminal outputs a first output current depending on a difference between the first current and the first bias current. The current generating circuit generates a third current which has a sign opposite to the second current on the basis of the second current. The second bias current generator generates a second bias current. The second output terminal outputs a second output current depending on a difference between the third current and the second bias current.
摘要翻译： 提供了一种单差分转换电路，包括：分频器电路，第一和第二偏置电流发生器，第一和第二输出端子以及电流产生电路。 分频器电路接收包括DC分量和AC分量的输入电流，并分割输入电流以产生第一电流和第二电流。 第一偏置电流发生器产生第一偏置电流。 第一输出端子根据第一电流和第一偏置电流之间的差异输出第一输出电流。 电流产生电路基于第二电流产生具有与第二电流相反的符号的第三电流。 第二偏置电流发生器产生第二偏置电流。 第二输出端子根据第三电流和第二偏置电流之间的差异输出第二输出电流。
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公开(公告)号：US20230394303A1
公开(公告)日：2023-12-07
申请号：US18179467
申请日：2023-03-07
发明人： Mari MATSUMOTO , Masanori FURUTA
IPC分类号： G06N3/08
CPC分类号： G06N3/08
摘要： According to one embodiment, each of the client terminals includes a first processor configured to execute a learning process of machine learning model, extract a first parameter column from the machine learning model, change the arrangement of parameters, perform secret sharing with respect to the first parameter column, and transmit a first fragment parameter column. Each of the aggregated server device includes a second processor configured to receive first fragment parameter columns, change arrangement of fragment parameters, and execute an aggregation process. The machine learning model is updated based on parameters in a second parameter column decoded from second fragment parameter columns generated in the aggregated server devices.
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公开(公告)号：US20220004815A1
公开(公告)日：2022-01-06
申请号：US17180707
申请日：2021-02-19
发明人： Mari MATSUMOTO , Masanori FURUTA
摘要： A learning system according to an embodiment includes a model generation device and n calculation devices. The model generation device includes a splitting unit, a secret sharing unit, and a share transmission unit. The splitting unit splits m×n pieces of training data into n groups each including m training data pieces, the n groups corresponding to the respective n calculation devices on one-to-one basis. The secret sharing unit generates m distribution training data pieces for each of the n groups by distributing using a secret sharing scheme and generates distribution training data for each of the m training data pieces in an i-th group among the n groups, using an i-th element Pi among n elements P1, P2, . . . , Pi, . . . , Pn, by distributing using the secret sharing scheme. The share transmission unit transmits corresponding m distribution training data pieces to each of the n calculation devices.
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公开(公告)号：US20210097438A1
公开(公告)日：2021-04-01
申请号：US17014270
申请日：2020-09-08
发明人： Mari MATSUMOTO , Masanori FURUTA
摘要： According to one embodiment, an anomaly detection device includes predicted value calculation unit, an anomaly degree calculation unit, a second predicted value calculation unit, a determination value calculation unit, and an anomaly determination unit. The first predicted value calculation unit calculates a first model predicted value from a correlation model obtained by first machine learning, the anomaly degree calculation unit calculates an anomaly degree, the second predicted value calculation unit calculates a second model predicted value from a time series model obtained by second machine learning, the determination value calculation unit calculates a divergence degree, and the anomaly determination unit determines whether an anomaly occurs or not.
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公开(公告)号：US20170241807A1
公开(公告)日：2017-08-24
申请号：US15429653
申请日：2017-02-10
CPC分类号： G01D5/16 , H03F3/45179 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45528
摘要： A readout circuit has a first transistor which have a first terminal, a second terminal, and a control terminal, a second transistor having a first terminal, a second terminal, and a control terminal, a first variable resistance having a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor, a first resistance having a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor, a second resistance having a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line, and a second variable resistance which has a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.
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