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公开(公告)号：US20190108630A1
公开(公告)日：2019-04-11
申请号：US16206691
申请日：2018-11-30
Applicant: KLA-Tencor Corporation
Inventor： Jason Z. Lin , Allen Park , Ellis Chang , Richard Wallingford , Songnian Rong , Chetana Bhaskar
IPC: G06T7/00
Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.
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2.发明授权Inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer 有权检查晶片和/或预测在晶片上形成的器件的一个或多个特性公开(公告)号：US08948495B2
公开(公告)日：2015-02-03
申请号：US13783291
申请日：2013-03-02
Applicant: KLA-Tencor Corporation
Inventor： Gino Marcuccilli , Amir Widmann , Ellis Chang , John Robinson , Allen Park
CPC classification number: G06T7/0004 , G06T7/001 , G06T2207/10061 , G06T2207/30148
Abstract: Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.
Abstract translation: 提供了检查晶片和/或预测在晶片上形成的器件的一个或多个特性的方法。 一种方法包括获取用于多个印刷在晶片上的图像，每个图像通过在晶片上执行双重图案化平版印刷工艺而被印刷，并且包括两个或更多个以双重图案化平版印刷工艺的覆盖的标称值印刷的模具，以及一个或 更多地以覆盖层的调制值打印; 将以标称值印刷的多个印模获得的图像与以调制值印刷的多个印模获得的图像进行比较; 并且基于比较步骤的结果检测以调制值印刷的多个印模中的缺陷。
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公开(公告)号：US09910953B2
公开(公告)日：2018-03-06
申请号：US14356551
申请日：2014-03-04
Applicant: KLA-Tencor Corporation
Inventor： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70625 , G03F7/70633 , G03F7/70683 , H01L22/12 , H01L22/30
Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.
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公开(公告)号：US20180032662A1
公开(公告)日：2018-02-01
申请号：US15727477
申请日：2017-10-06
Applicant: KLA-Tencor Corporation
Inventor： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70625 , G03F7/70633 , G03F7/70683 , H01L22/12 , H01L22/30
Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.
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公开(公告)号：US20170161418A1
公开(公告)日：2017-06-08
申请号：US15437409
申请日：2017-02-20
Applicant: KLA-Tencor Corporation
Inventor： Allen Park , Ellis Chang , Prashant A. Aji , Steven R. Lange
CPC classification number: G06F17/5068 , G01N21/9501 , G06F17/50 , G06F17/5009 , G06F2217/12 , H01L22/12 , H01L2924/0002 , H01L2924/00
Abstract: Various embodiments for using three-dimensional representations for defect-related applications are provided. One computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe includes generating a three-dimensional representation of one or more layers of a wafer based on design data. The method also includes determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation.
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Patent Agency Ranking
公开(公告)号：US08826200B2
公开(公告)日：2014-09-02
申请号：US13893267
申请日：2013-05-13
Applicant: KLA-Tencor Corporation
Inventor： Allen Park , Ellis Chang
IPC: G06F17/50
CPC classification number: G06F17/5045 , G01N21/956 , G06F17/5081 , G06F2217/14
Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.
Abstract translation: 提供了一种用于对晶片上的缺陷进行合并的方法和系统。 一种方法包括识别在晶片上制造的器件层的设计领域，其对于制造器件的制造不是至关重要的，并且通过从该设计中消除所识别的区域中的特征，从而为该层产生改变的设计 层。 该方法还包括使用改变的设计将层上检测到的缺陷分组成组，使得每个组中的缺陷的改变设计中的特征至少相似。
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公开(公告)号：US20140199791A1
公开(公告)日：2014-07-17
申请号：US14083126
申请日：2013-11-18
Applicant: KLA-Tencor Corporation
Inventor： Allen Park , Ellis Chang , Michael Adel , Kris Bhaskar , Ady Levy , Amir Widmann , Mark Wagner , Songnian Rong
CPC classification number: H01L22/12 , G06F17/5081
Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.
Abstract translation: 通用的基于目标的检测驱动度量包括设计多个通过检测工具测量的通用度量目标并且可以用计量工具测量，使用设计数据识别晶片的至少一个管芯内的多个检查特征，将多个通用目标 在晶片的至少一个模具内，每个通用目标被设置为至少接近所识别的可检查特征之一，用检查工具检查包含一个或多个通用目标的区域，以识别一个或多个异常通用目标 检查区域具有检查工具，并且响应于在被检查区域中识别一个或多个异常通用目标，对所述一个或多个异常通用度量目标与计量工具执行一个或多个计量过程。
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公开(公告)号：US20130318485A1
公开(公告)日：2013-11-28
申请号：US13893267
申请日：2013-05-13
Applicant: KLA-Tencor Corporation
Inventor： Allen Park , Ellis Chang
IPC: G06F17/50
CPC classification number: G06F17/5045 , G01N21/956 , G06F17/5081 , G06F2217/14
Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.
Abstract translation: 提供了一种用于对晶片上的缺陷进行合并的方法和系统。 一种方法包括识别在晶片上制造的器件层的设计领域，其对于制造器件的制造不是至关重要的，并且通过从该设计中消除所识别的区域中的特征，从而为该层产生改变的设计 层。 该方法还包括使用改变的设计将层上检测到的缺陷分组成组，使得每个组中的缺陷的改变设计中的特征至少相似。
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公开(公告)号：US09576861B2
公开(公告)日：2017-02-21
申请号：US14083126
申请日：2013-11-18
Applicant: KLA-Tencor Corporation
Inventor： Allen Park , Ellis Chang , Michael Adel , Kris Bhaskar , Ady Levy , Amir Widmann , Mark Wagner , Songnian Rong
CPC classification number: H01L22/12 , G06F17/5081
Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.
Abstract translation: 通用的基于目标的检测驱动度量包括设计多个通过检测工具测量的通用度量目标并且可以用计量工具测量，使用设计数据识别晶片的至少一个管芯内的多个检查特征，将多个通用目标 在晶片的至少一个模具内，每个通用目标被设置为至少接近所识别的可检查特征之一，用检查工具检查包含一个或多个通用目标的区域，以识别一个或多个异常通用目标 检查区域具有检查工具，并且响应于在被检查区域中识别一个或多个异常通用目标，对所述一个或多个异常通用度量目标与计量工具执行一个或多个计量过程。
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公开(公告)号：US09170209B1
公开(公告)日：2015-10-27
申请号：US14053193
申请日：2013-10-14
Applicant: KLA-Tencor Corporation
Inventor： Ellis Chang , Amir Widmann , Allen Park
CPC classification number: G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
Abstract translation: 检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，通过执行检查扫描来检查所产生的护理区域内的缺陷 每个生成的护理区域，其中检查扫描包括低阈值或高灵敏度检查扫描，识别具有大于使用缺陷检查技术的所选覆盖规格的测量的覆盖误差的半导体晶片的预定图案的覆盖位置 将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置，以及生成计量取样 基于确定的位置进行计划。
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