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1.发明公开公开(公告)号：US20230263070A1
公开(公告)日：2023-08-17
申请号：US18003913
申请日：2020-12-31
发明人： Guozhong Xing , Di Wang , Huai Lin , Long Liu , Yu Liu , Hangbing Lv , Changqing Xie , Ling Li , Ming Liu
CPC分类号： H10N50/10 , H10B61/22 , H10N50/85 , G11C11/161
摘要： The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.
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公开(公告)号：US11223013B2
公开(公告)日：2022-01-11
申请号：US16489266
申请日：2017-02-28
发明人： Qi Liu , Xiaolong Zhao , Sen Liu , Ming Liu , Hangbing Lv , Shibing Long , Yan Wang , Facai Wu
IPC分类号： H01L45/00
摘要： The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
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公开(公告)号：US11205750B2
公开(公告)日：2021-12-21
申请号：US16786346
申请日：2020-02-10
发明人： Qing Luo , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu
摘要： The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
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公开(公告)号：US10665780B2
公开(公告)日：2020-05-26
申请号：US16085400
申请日：2016-03-18
发明人： Ming Liu , Qing Luo , Xiaoxin Xu , Hangbing Lv , Shibing Long , Qi Liu
摘要： A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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公开(公告)号：US10475807B2
公开(公告)日：2019-11-12
申请号：US15503833
申请日：2014-09-25
发明人： Zongliang Huo , Ming Liu , Lei Jin
IPC分类号： H01L27/11578 , H01L27/11582 , H01L49/02
摘要： A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings. In accordance with the three-dimensional memory manufacturing method of the present invention, the deep trenches of word-line in the TCAT three-dimensional device are replaced with deep-hole etching to realize the same function, thereby improving the integration density, simplifying the etching process of stacked structure, and maintaining the control performance of the metal gate.
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公开(公告)号：US09779836B2
公开(公告)日：2017-10-03
申请号：US15125326
申请日：2014-03-12
发明人： Chong Bi , Shibing Long , Ming Liu
CPC分类号： G11C19/0858 , G11C11/1675 , G11C11/18 , G11C11/5607 , G11C19/0808 , G11C19/0816 , G11C19/0825 , G11C19/0841 , G11C19/085
摘要： The present disclosure relates to the technical field of information data storage and processing. There is provided a method for regulating magnetic multi-domain state, comprising: when a current is applied to a magnetic thin film, applying an additional external magnetic field having a magnetic field strength of 0 to 4×105 A/m to regulate magnetization state of the magnetic thin film; wherein the current is configured to drive movements of a magnetic domain of the magnetic multi-domain states in the magnetic thin film, and the external magnetic field is configured to regulate generation of new magnetic domain in the magnetic thin film and state of the magnetic domain during the movement, so that the magnetic thin film is in a stable magnetic multi-domain state. Such a multi-domain state can't be affected by a higher or lower current and keeps stable when the current is removed. Such a method may be used for magnetic memory or spin-logic device to implement a nonvolatile multi-valued storage, multi-bits logic operation, or neuromorphic computing.
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公开(公告)号：US20170092374A1
公开(公告)日：2017-03-30
申请号：US15125326
申请日：2014-03-12
发明人： Chong Bi , Shibing Long , Ming Liu
IPC分类号： G11C19/08
CPC分类号： G11C19/0858 , G11C11/1675 , G11C11/18 , G11C11/5607 , G11C19/0808 , G11C19/0816 , G11C19/0825 , G11C19/0841 , G11C19/085
摘要： The present disclosure relates to the technical field of information data storage and processing. There is provided a method for regulating magnetic multi-domain state, comprising: when a current is applied to a magnetic thin film, applying an external magnetic field having a magnetic field strength of 0 to 4×105 A/m to regulate magnetization state of the magnetic thin film; wherein the current is configured to drive movements of a magnetic domain of the magnetic multi-domain states in the magnetic thin film, and the external magnetic field is configured to regulate generation of new magnetic domain in the magnetic thin film and state of the magnetic domain during the movement, so that the magnetic thin film is in a stable magnetic multi-domain state. Such a multi-domain state can't be affected by a higher or lower current and may be kept to be stable when the current is removed. Such a method may be used for current magnetic memory and to operate the magnetization stage of the spin-logic device in the future to implement a nonvolatile multi-valued storage and multi-bits logic operation.
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8.发明授权公开(公告)号：US09442230B2
公开(公告)日：2016-09-13
申请号：US14144222
申请日：2013-12-30
发明人： Hailiang Li , Changqing Xie , Ming Liu , Dongmei Li , Lina Shi , Xiaoli Zhu
CPC分类号： G02B5/1871 , G02B5/1809 , G02B5/1838 , G02B5/1857 , G02B2005/1804 , G03F7/0757 , G03F7/2059 , G03F7/40
摘要： A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns.
摘要翻译： 公开了一种制造亚波长极紫外金属透射光栅的方法。 在一个方面，该方法包括在硅衬底的背表面上形成氮化硅自支撑膜窗，其两面被抛光，然后用电子束在衬底的前表面上旋涂氮化硅膜 抵制HSQ。 然后，在HSQ上执行电子束直接写入曝光，显影和固定以形成围绕光栅线图案的多个光栅线图案和环形图案。 然后通过磁控溅射在基板的前表面上沉积铬材料。 然后，移除环形图案内的铬材料。 然后，通过原子层沉积在基板的前表面上生长金材料。 最后，除去环形图案之外的铬材料上的金材料以及光栅线图案之间和之间的金材料，从而仅将金材料保留在光栅线图案的侧壁上。
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9.发明授权Method for manufacturing ordered nanowire array of NiO doped with Pt in situ 有权用于原位掺杂Pt的NiO有序纳米线阵列的制备方法公开(公告)号：US09418843B2
公开(公告)日：2016-08-16
申请号：US14760890
申请日：2013-01-17
发明人： Dongmei Li , Xin Chen , Shengfa Liang , Jiebin Niu , Peiwen Zhang , Yu Liu , Xiaojing Li , Shuang Zhan , Hao Zhang , Qing Luo , Changqing Xie , Ming Liu
CPC分类号： H01L21/02565 , B82Y10/00 , B82Y40/00 , G01N33/004 , G01N33/005 , H01L21/02422 , H01L21/02581 , H01L21/02603 , H01L21/02614 , H01L21/465 , Y02A50/243
摘要： The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and H2 are greatly improved.
摘要翻译： 本公开提供了一种用于制造原位掺杂有Pt的NiO的有序纳米线阵列的方法，包括：在耐高温和绝缘的衬底上生长Ni层; 在Ni层上施加光致抗蚀剂，通过在光致抗蚀剂上施加电子束蚀刻来图案化有序纳米线阵列的图案区域，在有序纳米线阵列的图案区域上生长Ni，用丙酮剥离光致抗蚀剂并蚀刻 Ni层，以便蚀刻生长在衬底表面上的Ni层，并将Ni留在有序纳米线阵列的图案区上以形成有序的Ni纳米线阵列; 将有序的Ni纳米线阵列浸入H2PtCl6溶液中，通过置换反应置换Ni纳米线阵列上的Pt; 并在氧化炉中氧化附着有Pt的Ni纳米线阵列，以获得掺杂有Pt的NiO的有序纳米线阵列。 本发明简单实用，掺杂传感器对CO和H2气体的灵敏度和可靠性大大提高。
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公开(公告)号：US20240013826A1
公开(公告)日：2024-01-11
申请号：US18251699
申请日：2021-10-13
发明人： Guozhong Xing , Di Wang , Long Liu , Huai Lin , Ming Liu
CPC分类号： G11C11/161 , H10B61/22 , H10N50/20 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G06F17/16
摘要： Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.
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