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    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME
    4.
    发明申请
    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME 有权
    用于集成电路封装的电气互连及其制造方法

    公开(公告)号：US20160211208A1

    公开(公告)日：2016-07-21

    申请号：US15082501

    申请日：2016-03-28

    Applicant: General Electric Company

    Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

    Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

    Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电 它们之间的连接。 上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。 互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。

    Electrical interconnect for an integrated circuit package and method of making same
    6.
    发明授权
    Electrical interconnect for an integrated circuit package and method of making same 有权

    公开(公告)号：US10068840B2

    公开(公告)日：2018-09-04

    申请号：US15618660

    申请日：2017-06-09

    Applicant: General Electric Company

    Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

    Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.

    Electrical interconnect for an integrated circuit package and method of making same
    7.
    发明授权
    Electrical interconnect for an integrated circuit package and method of making same 有权
    集成电路封装的电气互连及其制造方法

    公开(公告)号：US09570376B2

    公开(公告)日：2017-02-14

    申请号：US14625744

    申请日：2015-02-19

    Applicant: General Electric Company

    Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

    Abstract translation: 芯片封装包括：第一基板，其具有在其第一表面上形成的至少一个电路层，安装在第一基板的与第一表面相对的第二表面上的第一裸片;以及互连组件，其包括设置在第一基板上的上下导电层 绝缘基板，其中互连组件的上导电层固定到第一基板的第二表面并电连接到第一基板的至少一个电路层。 第二基板位于与第一基板相对的第一模具的一侧上，以便将模具定位在第一和第二基板之间，第二基板具有形成在其面向外的第一表面上的至少一个电路层， 连接到互连组件和第一模具的至少一个下导电层。

    Electrical interconnect for an integrated circuit package and method of making same
    8.
    发明授权
    Electrical interconnect for an integrated circuit package and method of making same 有权
    集成电路封装的电气互连及其制造方法

    公开(公告)号：US09299647B2

    公开(公告)日：2016-03-29

    申请号：US14181105

    申请日：2014-02-14

    Applicant: General Electric Company

    Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

    Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

    Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电 它们之间的连接。 上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。 互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。

    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME
    9.
    发明申请
    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME 有权
    用于集成电路封装的电气互连及其制造方法

    公开(公告)号：US20150171036A1

    公开(公告)日：2015-06-18

    申请号：US14625744

    申请日：2015-02-19

    Applicant: General Electric Company

    Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498

    CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

    Abstract translation: 芯片封装包括：第一基板，其具有在其第一表面上形成的至少一个电路层，安装在第一基板的与第一表面相对的第二表面上的第一裸片;以及互连组件，其包括设置在第一基板上的上下导电层 绝缘基板，其中互连组件的上导电层固定到第一基板的第二表面并电连接到第一基板的至少一个电路层。 第二基板位于与第一基板相对的第一模具的一侧上，以便将模具定位在第一和第二基板之间，第二基板具有形成在其面向外的第一表面上的至少一个电路层， 连接到互连组件和第一模具的至少一个下导电层。

    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME
    10.
    发明申请
    ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME 有权
    用于集成电路封装的电气互连及其制造方法

    公开(公告)号：US20140159213A1

    公开(公告)日：2014-06-12

    申请号：US14181105

    申请日：2014-02-14

    Applicant: General Electric Company

    Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

    Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

    Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电 它们之间的连接。 上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。 互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。

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