System and Method for Integration of Hybrid Pipeline
    1.
    发明申请
    System and Method for Integration of Hybrid Pipeline 有权
    混合管道整合系统与方法

    公开(公告)号:US20150009059A1

    公开(公告)日:2015-01-08

    申请号:US14021735

    申请日:2013-09-09

    Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

    Abstract translation: 系统包括作为处理输入信号的第一级的流水线模数转换器和用于处理输入信号的逐次逼近寄存器(SAR)模数转换器作为第二级。 SAR模数转换器包括功率调整元件,用于调整SAR模数转换器的参考电压,以匹配流水线模数转换器的满量程电压。

    Pipelined interpolating sub-ranging SAR analog-to-digital converter
    3.
    发明授权
    Pipelined interpolating sub-ranging SAR analog-to-digital converter 有权
    流水线内插子范围SAR模数转换器

    公开(公告)号:US09356616B1

    公开(公告)日:2016-05-31

    申请号:US14816387

    申请日:2015-08-03

    Abstract: A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.

    Abstract translation: 一个多位每周期逐次逼近寄存器(SAR)模数转换器(ADC)可以对输入信号进行采样,以包含信号的收缩子范围连续近似采样信号,并输出对应于 子范围 子范围级可以通过在绑定子范围的一对过零信号之间进行采样和内插来在子范围上继续量化。 过零信号可以取自SAR前置放大器输出。 子范围过程可以在多个阶段递归流水线以增加吞吐量和效率。

    INTEGRATED CIRCUITS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY
    5.
    发明申请
    INTEGRATED CIRCUITS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY 有权
    集成电路与通用串行总线2.0和嵌入式通用串行总线2连接

    公开(公告)号:US20160162430A1

    公开(公告)日:2016-06-09

    申请号:US14590780

    申请日:2015-01-06

    Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

    Abstract translation: 提供集成电路。 集成电路包括通信模式确定电路,其被配置为检测第一数据线和第二数据线中的一个或两个的信号电平,并且确定第一数据线和第二数据线的通信模式是否是第一数据线 通用串行总线(USB)通信模式或第二USB通信模式。 集成电路还包括基于所确定的通信模式而配置为以多种模式之一操作的第一收发器电路。 集成电路还包括被配置为基于所确定的通信模式在多种模式之一中操作的第二收发器电路。 所述第一USB通信模式的最大信号电平大于所述第二USB通信模式的最大信号电平。

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