公开(公告)号：US09356616B1

公开(公告)日：2016-05-31

申请号：US14816387

申请日：2015-08-03

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Xin Jin ,  Chia-Jen Hsu

IPC: H03M1/14 ,  H03M1/44 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/445 ,  H03M1/141 ,  H03M1/144 ,  H03M1/145 ,  H03M1/204 ,  H03M1/46

Abstract: A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.

Abstract translation: 一个多位每周期逐次逼近寄存器（SAR）模数转换器（ADC）可以对输入信号进行采样，以包含信号的收缩子范围连续近似采样信号，并输出对应于 子范围 子范围级可以通过在绑定子范围的一对过零信号之间进行采样和内插来在子范围上继续量化。 过零信号可以取自SAR前置放大器输出。 子范围过程可以在多个阶段递归流水线以增加吞吐量和效率。