公开(公告)号：US09118339B2

公开(公告)日：2015-08-25

申请号：US13930922

申请日：2013-06-28

Applicant: Broadcom Corporation

Inventor： Ayaskant Shrivastava ,  Chun-Ying Chen

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1235 ,  H03M1/164 ,  H03M1/186

Abstract: The present disclosure provides for an analog-to-digital converter (ADC) which selectively compresses an analog input signal to improve noise performance and dynamic input range. The ADC selectively scales an analog input signal when it is closer to an expected value of one or more signal metrics more than when it is further from the expected value of the one or more signal metrics. For example, during the conversion process, the ADC amplifies the analog input signal when it is closer to a mean value μ by a gain factor while selectively adjusting the gain factor when the analog input signal is further from its mean value μ to selectively compress the analog input signal. This selective compression improves input noise performance and dynamic input range of the ADC when compared to the conventional ADC.

Abstract translation: 本公开提供了一种模数转换器（ADC），其选择性地压缩模拟输入信号以改善噪声性能和动态输入范围。 当模拟输入信号比一个或多个信号度量的期望值进一步更接近于一个或多个信号度量的期望值时，ADC选择性地缩放模拟输入信号。 例如，在转换过程中，当模拟输入信号更接近于平均值μ时，ADC将放大增益因子，同时当模拟输入信号进一步从其平均值μ选择性地调节增益因子时，ADC选择性地压缩 模拟输入信号。 与常规ADC相比，该选择性压缩可提高ADC的输入噪声性能和动态输入范围。

公开(公告)号：US20140340252A1

公开(公告)日：2014-11-20

申请号：US13930922

申请日：2013-06-28

Applicant: Broadcom Corporation

Inventor： Ayaskant SHRIVASTAVA ,  Chun-Ying Chen

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1235 ,  H03M1/164 ,  H03M1/186

Abstract: The present disclosure provides for an analog-to-digital converter (ADC) which selectively compresses an analog input signal to improve noise performance and dynamic input range. The ADC selectively scales an analog input signal when it is closer to an expected value of one or more signal metrics more than when it is further from the expected value of the one or more signal metrics. For example, during the conversion process, the ADC amplifies the analog input signal when it is closer to a mean value μ by a gain factor while selectively adjusting the gain factor when the analog input signal is further from its mean value μ to selectively compress the analog input signal. This selective compression improves input noise performance and dynamic input range of the ADC when compared to the conventional ADC.

Abstract translation: 本公开提供了一种模数转换器（ADC），其选择性地压缩模拟输入信号以改善噪声性能和动态输入范围。 当模拟输入信号比一个或多个信号度量的期望值进一步更接近于一个或多个信号度量的期望值时，ADC选择性地缩放模拟输入信号。 例如，在转换过程中，当模拟输入信号更接近于平均值μ时，ADC将放大增益因子，同时当模拟输入信号进一步从其平均值μ选择性地调节增益因子时，ADC选择性地压缩 模拟输入信号。 与常规ADC相比，该选择性压缩可提高ADC的输入噪声性能和动态输入范围。

公开(公告)号：US08878707B1

公开(公告)日：2014-11-04

申请号：US13967819

申请日：2013-08-15

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Massimo Brandolini ,  Wei-Te Chou

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/1245 ,  H03M1/164

Abstract: A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Abstract translation: 系统包括第一存储元件，用于存储用于无SHA阶段的第一采样通道的输入信号。 第一开关与第一存储元件连接，第一开关用于控制第一存储元件何时存储用于在第一采样通道上采样的输入信号。 第二开关与第一开关串联连接，第二开关用于控制用于对存储在第一采样通道的第一存储元件上的输入信号进行采样的实例。

公开(公告)号：US20150009059A1

公开(公告)日：2015-01-08

申请号：US14021735

申请日：2013-09-09

Applicant: Broadcom Corporation

Inventor： Chun-Ying Chen ,  Wei-Ta Shih ,  Rong Wu ,  Young Shin ,  Karthik Raviprakash ,  Tao Wang ,  Chia-Jen Hsu ,  Tianwei Li

IPC: H03M1/12

CPC classification number: H03M1/187 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1215 ,  H03M1/144 ,  H03M1/164

Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

Abstract translation: 系统包括作为处理输入信号的第一级的流水线模数转换器和用于处理输入信号的逐次逼近寄存器（SAR）模数转换器作为第二级。 SAR模数转换器包括功率调整元件，用于调整SAR模数转换器的参考电压，以匹配流水线模数转换器的满量程电压。

公开(公告)号：US09379726B1

公开(公告)日：2016-06-28

申请号：US14638532

申请日：2015-03-04

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Massimo Brandolini ,  Wei Li

IPC: H03M1/38 ,  H03M1/00 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/125 ,  H03M1/466

Abstract: The present disclosure is directed to a system and method for adjusting a conversion speed of an asynchronous SAR ADC based on a margin of time between when a conversion of a sample of an analog signal completes and a next sample of the analog signal is taken, referred to as a “conversion time margin.” The system and method reduce the conversion speed of an asynchronous SAR ADC when the conversion time margin permits to reduce the amount of power consumed and/or noise produced by the asynchronous SAR ADC.

Abstract translation: 本公开涉及一种用于基于模拟信号的样本的转换完成与模拟信号的下一个采样之间的时间间隔来调整异步SAR ADC的转换速度的系统和方法， 作为“转换时间裕度”。当转换时间裕度允许减少由异步SAR ADC产生的功耗量和/或噪声时，该系统和方法降低了异步SAR ADC的转换速度。

公开(公告)号：US09030344B2

公开(公告)日：2015-05-12

申请号：US14021735

申请日：2013-09-09

Applicant: Broadcom Corporation

Inventor： Chun-Ying Chen ,  Wei-Ta Shih ,  Rong Wu ,  Young Shin ,  Karthik Raviprakash ,  Tao Wang ,  Chia-Jen Hsu ,  Tianwei Li

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/06

CPC classification number: H03M1/187 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1215 ,  H03M1/144 ,  H03M1/164

Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

Abstract translation: 系统包括作为处理输入信号的第一级的流水线模数转换器和用于处理输入信号的逐次逼近寄存器（SAR）模数转换器作为第二级。 SAR模数转换器包括功率调整元件，用于调整SAR模数转换器的参考电压，以匹配流水线模数转换器的满量程电压。

公开(公告)号：US08730073B1

公开(公告)日：2014-05-20

申请号：US13738557

申请日：2013-01-10

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Jiangfeng Wu

IPC: H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/167

Abstract: A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Abstract translation: 通过流水线模数转换器（ADC）对模拟信号进行数字化的方法可以包括将样本子级，量子化级和放大级分别流水线到ADC通道。 在多个流水线阶段的第一阶段中，可以将时钟相位分配给ADC通道，包括采样时钟相位，量化时钟相位和放大时钟相位，使得量化时钟相位与采样时钟相位不重叠， 放大时钟相位。 可以通过为多个ADC通道的子级产生多个参考时钟相位并且将采样时钟相位，量化时钟相位和放大时钟相位的分配交织到参考时钟相位中，从而促进非重叠特征 多条车道。