公开(公告)号：US09118339B2

公开(公告)日：2015-08-25

申请号：US13930922

申请日：2013-06-28

Applicant: Broadcom Corporation

Inventor： Ayaskant Shrivastava ,  Chun-Ying Chen

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1235 ,  H03M1/164 ,  H03M1/186

Abstract: The present disclosure provides for an analog-to-digital converter (ADC) which selectively compresses an analog input signal to improve noise performance and dynamic input range. The ADC selectively scales an analog input signal when it is closer to an expected value of one or more signal metrics more than when it is further from the expected value of the one or more signal metrics. For example, during the conversion process, the ADC amplifies the analog input signal when it is closer to a mean value μ by a gain factor while selectively adjusting the gain factor when the analog input signal is further from its mean value μ to selectively compress the analog input signal. This selective compression improves input noise performance and dynamic input range of the ADC when compared to the conventional ADC.

Abstract translation: 本公开提供了一种模数转换器（ADC），其选择性地压缩模拟输入信号以改善噪声性能和动态输入范围。 当模拟输入信号比一个或多个信号度量的期望值进一步更接近于一个或多个信号度量的期望值时，ADC选择性地缩放模拟输入信号。 例如，在转换过程中，当模拟输入信号更接近于平均值μ时，ADC将放大增益因子，同时当模拟输入信号进一步从其平均值μ选择性地调节增益因子时，ADC选择性地压缩 模拟输入信号。 与常规ADC相比，该选择性压缩可提高ADC的输入噪声性能和动态输入范围。