公开(公告)号：US20140333353A1

公开(公告)日：2014-11-13

申请号：US13900078

申请日：2013-05-22

Applicant: Broadcom Corporation

Inventor： Dae Woon Kang

IPC: H03L7/06

CPC classification number: H03L7/00

Abstract: Disclosed are various embodiments for a clock and data recovery (CDR) system. The CDR system comprises a transition detection stage and a clock recovery stage. The transition detection stage is responsible for receiving the data signal and detecting whether a transition exists in the data signal by oversampling the data signal. The clock recovery stage generates a recovery clock based on whether there is a transition in the data signal.

Abstract translation: 公开了用于时钟和数据恢复（CDR）系统的各种实施例。 CDR系统包括转换检测级和时钟恢复级。 转换检测级负责接收数据信号，并通过过采样数据信号来检测数据信号中是否存在转换。 时钟恢复阶段基于数据信号中是否存在转换来产生恢复时钟。

公开(公告)号：US09836420B2

公开(公告)日：2017-12-05

申请号：US14645112

申请日：2015-03-11

Applicant: BROADCOM CORPORATION

Inventor： Dae Woon Kang ,  Desheng Ma ,  Derek Hing Sang Tam ,  Chia-Jen Hsu ,  Preeti Mulage

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/387 ,  G06F13/4282 ,  G06F2213/0042

Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.