公开(公告)号：US20140317425A1

公开(公告)日：2014-10-23

申请号：US13864723

申请日：2013-04-17

Applicant: APPLE INC.

Inventor： Wei-Han Lien ,  Gerard R. Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R. Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

公开(公告)号：US20130103906A1

公开(公告)日：2013-04-25

申请号：US13709649

申请日：2012-12-10

Applicant: Apple Inc.

Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh B. Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。 折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

公开(公告)号：US09411360B2

公开(公告)日：2016-08-09

申请号：US14153296

申请日：2014-01-13

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Wei-Han Lien ,  Shih-Chieh R. Wen

IPC: G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

Abstract translation: 一种用于管理时钟信号频率变化的系统，包括被配置为输出时钟信号的时钟发生器，耦合到时钟发生器的输出的时钟分配器，被配置为选择时钟信号的频率的处理器，以及 一个时钟管理电路。 时钟管理电路可以被配置为设置时钟发生器以将时钟信号调整到所选择的频率。 时钟管理电路还可以被配置为响应于以所选频率稳定的时钟信号的确定，在多个步骤中调整时钟分频器的除数值。 可以在多个步骤中的每个步骤期间选择新的除数值，并且每个步骤可以在给定时间段之后发生。

公开(公告)号：US09294103B2

公开(公告)日：2016-03-22

申请号：US14180976

申请日：2014-02-14

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Shih-Chieh R. Wen ,  Toshinari Takayanagi ,  Wei-Han Lien

IPC: H03L7/06 ,  H03L7/08 ,  H03K5/00

CPC classification number: H03L7/08 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  H03K5/00006 ,  H03L7/10 ,  H03L2207/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.

Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。

公开(公告)号：US20170068575A1

公开(公告)日：2017-03-09

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, JR. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。

公开(公告)号：US20150198966A1

公开(公告)日：2015-07-16

申请号：US14153296

申请日：2014-01-13

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Wei-Han Lien ,  Shih-Chieh R. Wen

IPC: G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

Abstract translation: 一种用于管理时钟信号频率变化的系统，包括被配置为输出时钟信号的时钟发生器，耦合到时钟发生器的输出的时钟分配器，被配置为选择时钟信号的频率的处理器，以及 一个时钟管理电路。 时钟管理电路可以被配置为设置时钟发生器以将时钟信号调整到所选择的频率。 时钟管理电路还可以被配置为响应于以所选频率稳定的时钟信号的确定，在多个步骤中调整时钟分频器的除数值。 可以在多个步骤中的每个步骤期间选择新的除数值，并且每个步骤可以在给定时间段之后发生。

公开(公告)号：US10401938B1

公开(公告)日：2019-09-03

申请号：US15483178

申请日：2017-04-10

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Ramesh B. Gunna ,  Shih-Chieh R. Wen ,  John H. Mylius

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for reaching power targets across different clock domains are described. In various embodiments, a first processor complex and a second processor complex operate while powered by a same, single power plane, but with respective clock domains. When a request is detected to change an operating mode of a particular core from one of the processor complexes to an operating mode which does not provide the worst-case power supply load on the single power plane, an amount of voltage margin to recover from the operational voltage is determined based on the second operating mode prior to granting the request and based on each other core in the complexes operating in respective current operating modes. An operational voltage less the determined voltage margin to recover is assigned to the processor complexes while different clock frequencies are assigned to the processor complexes.

公开(公告)号：US09541984B2

公开(公告)日：2017-01-10

申请号：US13910584

申请日：2013-06-05

Applicant: Apple Inc.

Inventor： Shih-Chieh R. Wen ,  Jason M. Kassoff ,  Wei-Han Lien

IPC: G01F1/32 ,  G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3278 ,  Y02D10/14 ,  Y02D10/157

Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.

Abstract translation: 包括一个或多个处理器，耦合到至少一个处理器的存储器，耦合到存储器的通信链路和电源管理单元的系统和方法。 电源管理单元可以被配置为检测至少一个处理器的不活动状态。 电源管理单元可以被配置为在处理器进入非活动状态之后的一个时间禁用通信链路，并且在处理器进入非活动状态之后的另一时间禁用该存储器。

公开(公告)号：US09928115B2

公开(公告)日：2018-03-27

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, Jr. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F12/084 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0813

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

公开(公告)号：US20150236705A1

公开(公告)日：2015-08-20

申请号：US14180976

申请日：2014-02-14

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Shih-Chieh R. Wen ,  Toshinari Takayanagi ,  Wei-Han Lien

IPC: H03L7/08 ,  H03K5/00

CPC classification number: H03L7/08 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  H03K5/00006 ,  H03L7/10 ,  H03L2207/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.

Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。