公开(公告)号：US07254084B2

公开(公告)日：2007-08-07

申请号：US11138344

申请日：2005-05-27

Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C5/14 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

公开(公告)号：US07043466B2

公开(公告)日：2006-05-09

申请号：US09739758

申请日：2000-12-20

Applicant: Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

Inventor： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC: G06N3/06 ,  G06N3/063 ,  G06N3/067 ,  G06N1/00 ,  G06F15/18

CPC classification number: G06N3/063

Abstract: The neural network processing system according to the present invention includes a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit.

Abstract translation: 根据本发明的神经网络处理系统包括存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。

公开(公告)号：US06667928B2

公开(公告)日：2003-12-23

申请号：US10132248

申请日：2002-04-26

Applicant: Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

Inventor： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

IPC: G11C700

CPC classification number: G11C29/028 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5004

Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.

Abstract translation: 公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量 产品和理性需求响应生产管理。 半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块， 第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性 电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

公开(公告)号：US5875347A

公开(公告)日：1999-02-23

申请号：US723012

申请日：1996-09-30

Applicant: Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

Inventor： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC: G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F15/00

CPC classification number: G06N3/063

Abstract: Herein disclosed is a data processing system having a memory packaged therein for realizing a largescale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

Abstract translation: 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5822267A

公开(公告)日：1998-10-13

申请号：US305528

申请日：1994-09-13

Applicant: Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

Inventor： Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

IPC: G11C5/14 ,  G11C7/00 ,  G11C7/12 ,  G11C8/00 ,  G11C8/10 ,  G11C11/4094 ,  H03K5/08 ,  H03K17/00 ,  H03K17/693 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0944

CPC classification number: G11C7/12 ,  G11C11/4094 ,  G11C11/413 ,  G11C5/14 ,  G11C5/147 ,  G11C8/10 ,  H03K17/693 ,  H03K19/00376 ,  H03K19/00384 ,  H03K19/017 ,  H03K19/01707 ,  H03K19/017518 ,  H03K19/09448 ,  H03K5/08 ,  H03K2217/0036

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

公开(公告)号：US5526313A

公开(公告)日：1996-06-11

申请号：US104508

申请日：1993-08-10

Applicant: Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

Inventor： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/147

Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

公开(公告)号：US5448526A

公开(公告)日：1995-09-05

申请号：US282311

申请日：1994-07-29

Applicant: Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

Inventor： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

IPC: G01R31/317 ,  G05F3/24 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C5/147 ,  G01R31/31715 ,  G05F3/24

Abstract: An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

Abstract translation: 在半导体集成电路中设置有用于产生位于外部电源电压和接地电压之间的电压的中间电压产生电路和用于产生内部电源电压并以该中间电压稳定的两个限压器电路。 即使外部电源电压或接地电压发生波动，也不会在外部电源电压工作的电路的逻辑阈值与内部电源电压的电路的逻辑阈值之间产生不同意见。

公开(公告)号：US5347492A

公开(公告)日：1994-09-13

申请号：US152387

申请日：1993-11-16

Applicant: Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

Inventor： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

IPC: G01R31/317 ,  G05F3/24 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C5/147 ,  G01R31/31715 ,  G05F3/24

Abstract: An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

公开(公告)号：US4837462A

公开(公告)日：1989-06-06

申请号：US130640

申请日：1987-12-09

Applicant: Takao Watanabe ,  Goro Kitukawa ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Takayuki Kawahara

Inventor： Takao Watanabe ,  Goro Kitukawa ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Takayuki Kawahara

IPC: G11C7/12 ,  G11C8/10 ,  H03K5/08 ,  H03K17/00 ,  H03K17/693 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0944

CPC classification number: G11C8/10 ,  G11C7/12 ,  H03K17/693 ,  H03K19/017 ,  H03K19/017518 ,  H03K19/09448 ,  H03K5/08 ,  H03K2217/0036

Abstract: The invention relates to a semiconductor device which has a high density of integration and of which a low power consumption is required. The semiconductor device prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit and a succeeding circuit are provided with different reference voltages. The semiconductor device is constructed of a circuit which includes a bipolar transistor and an insulated-gate field effect transistor, and which operates with reference to one or more voltages, at least one of the reference voltages having a voltage value different from a reference operating voltage of a preceding circuit. A first switching circuit is interposed between a first reference voltage and an input node of a driver circuit, and a second switching circuit is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the seconding circuit switch is turned "on" while the first switching circuit is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switching circuit is turned "off" while the first switching circuit is turned "on". The semiconductor device is suited to high-density DRAM and SRAM circuits which use voltage limiters.

公开(公告)号：US4796234A

公开(公告)日：1989-01-03

申请号：US927144

申请日：1986-11-05

Applicant: Kiyoo Itoh ,  Yoshiki Kawajiri ,  Katsutaka Kimura ,  Ryoichi Hori ,  Jun Etoh

Inventor： Kiyoo Itoh ,  Yoshiki Kawajiri ,  Katsutaka Kimura ,  Ryoichi Hori ,  Jun Etoh

IPC: G11C11/409 ,  G11C7/06 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4091 ,  G11C7/00

CPC classification number: G11C8/14 ,  G11C11/4091 ,  G11C7/06 ,  G11C8/12

Abstract: It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.

Abstract translation: 可以想到实现具有大存储容量，高集成度和低功耗的半导体存储器。 公开了一种半导体存储器，包括多个块，每个块具有存储单元阵列和读出放大器，用于差分放大从阵列读出的信号，其中由所述感测中的N沟道MOS晶体管组成的公共驱动线 放大器和由感测放大器中的P沟道MOS晶体管组成的放大器的公共驱动线连接在不同的块之间。