公开(公告)号：US07613032B2

公开(公告)日：2009-11-03

申请号：US12027548

申请日：2008-02-07

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/412

摘要： A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括第一反相器和第二反相器，连接到第一反相器的输出端的第一存储节点和第二反相器的输入端，以及连接到第一反相器的第二存储节点 第一反相器的输入端子和第二反相器的输出端子，连接到存储单元的字线和分别连接到存储单元的多个位线。 输入数据被写入所选择的存储单元，并且在写入操作中从未选择的存储单元读取的数据被再次写入未选择的存储单元。

公开(公告)号：US20090213635A1

公开(公告)日：2009-08-27

申请号：US12430253

申请日：2009-04-27

申请人： Akihito Tohata ,  Tomoaki Yabe

发明人： Akihito Tohata ,  Tomoaki Yabe

IPC分类号： G11C5/06 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

摘要翻译： 一种半导体存储器件包括第一和第二单元阵列，其具有排列在行和列方向上的存储单元，连接到沿列方向排列的存储单元的第一和第二位线以及连接到列方向的第一和第二读出放大器 第一位，第二位线。 该装置还包括第一和第二虚拟单元阵列，其具有排列在行和列方向上的虚设单元，连接到沿行方向排列的虚拟单元的虚拟字线，连接到行方向的第一和第二虚拟位线 虚拟单元，沿列方向排列并接收来自虚拟字线的输出，以及第一和第二读出放大器激活电路，其根据从第一和第二虚拟位线输出的第一和第二控制信号激活第一，第二读出放大器 ， 分别。

公开(公告)号：US20080232148A1

公开(公告)日：2008-09-25

申请号：US12052020

申请日：2008-03-20

申请人： Tomoaki YABE

发明人： Tomoaki YABE

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/04 ,  G11C15/046 ,  G11C29/846

摘要： A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

摘要翻译： 一种半导体存储器件，包括：第一存储器，其中输入第一地址和第一输入数据，并且将第一输出数据输入到第一地址作为搜索地址输入的内容寻址存储器，并且执行搜索 确定第一地址和缺陷地址是否彼此一致，并且当第一地址和有缺陷地址彼此一致时，输出第二地址和控制信号，第二存​​储器，当第二地址被输入时 输出对应于第二地址的冗余数据，以及多路复用器，当输入控制信号时，将输出数据从第一输出数据切换到冗余数据，并将冗余数据输出到输入/输出端。

公开(公告)号：US20070127286A1

公开(公告)日：2007-06-07

申请号：US11538983

申请日：2006-10-05

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.

摘要翻译： 半导体存储器件包括多个字线，第一和第二位线，连接到第一和第二位线的多个存储器单元，连接到第一位线的一端和一端的差分放大器 第二位线的基准电流产生电路，连接到第二位线的另一端并产生小于存储单元的单元电流的参考电流;以及虚拟字线，其连接到 参考电流产生电路，以激活参考电流产生电路以便读取数据。

公开(公告)号：US20050232058A1

公开(公告)日：2005-10-20

申请号：US10918642

申请日：2004-08-16

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/412

CPC分类号： G11C11/412 ,  Y10S257/903 ,  Y10S257/904

摘要： A semiconductor integrated circuit device is configured by eight transistors including the six transistors configuring the data holding section and the two NMOS transistors configuring the reading stage. The threshold voltage of the NMOS transistors configuring the reading stage is set low and the threshold voltage of the six transistors configuring the data holding section is set higher than the threshold voltage of the NMOS transistors configuring the reading stage. The cell current flowing from the bit line to the ground terminal can be set large and the large static noise margin (SNM) can be attained.

摘要翻译： 半导体集成电路器件由包括配置数据保持部分的六个晶体管和配置读取级的两个NMOS晶体管的八个晶体管构成。 配置读取级的NMOS晶体管的阈值电压被设置为低，并且将构成数据保持部分的六个晶体管的阈值电压设置为高于构成读取级的NMOS晶体管的阈值电压。 可以将从位线流到接地端子的电池电流设定得较大，可以获得大的静态噪声容限（SNM）。

公开(公告)号：US6002631A

公开(公告)日：1999-12-14

申请号：US982534

申请日：1997-12-02

申请人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

发明人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/1045 ,  G11C8/12

摘要： Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.

摘要翻译： 偶数列布置在第一存储单元阵列（bank）中，奇数列排列在第二存储单元阵列（bank）中。 列地址信号通过缓冲器输入到加法器。 当从两个或多个列读出数据时，加法器产生地址值大于列地址信号的列地址信号。 加法器为第一列解码器提供列地址信号，用于寻址偶数列，并向第二列解码器提供用于寻址奇数列的列地址信号。 由于偶数列和奇数列排列在其分开的存储单元阵列中，所以从连续的两个或更多个列读出的数据不会彼此冲突。

公开(公告)号：US5426390A

公开(公告)日：1995-06-20

申请号：US323570

申请日：1994-10-17

申请人： Tomoaki Yabe ,  Masataka Matsui ,  Kouichi Satou

发明人： Tomoaki Yabe ,  Masataka Matsui ,  Kouichi Satou

IPC分类号： H03K5/1532 ,  H03K5/00 ,  H03K3/86

CPC分类号： H03K5/1532

摘要： In input transition detection pulse generators used in semiconductor memory devices, etc., in order to permit a designer to arbitrarily design the power supply voltage dependency of an output pulse width in accordance with use, a scheme is employed such that the functional block for detecting transition of an input or inputs to generate a pulse signal or signals, or the functional block for setting the width of each pulse signal is caused to have a function to generate pulse signals having different power supply voltage dependencies of pulse widths to perform a predetermined logical operation by a logical operation unit on the basis of pulse signals from the input transition detection pulse generation block or the pulse width setting block, thus to output a pulse having a pulse width optimum for a power supply voltage used. In place of the logical operation unit, an approach may be employed to select any one of a plurality of units as the input transition detection pulse generation block or the pulse width setting block by using a control signal to output a pulse having any pulse width. Further, the input transition pulse generation block or the pulse width setting block may be constructed to set at least one pulse width of pulses generated therefrom on the basis of a delay time generated by using an RC delay line.

摘要翻译： 在用于半导体存储器件等的输入转换检测脉冲发生器中，为了允许设计者根据使用任意地设计输出脉冲宽度的电源电压依赖性，采用一种方案，使得用于检测的功能块 导致用于产生脉冲信号或信号的输入或输入的转换或用于设置每个脉冲信号的宽度的功能块被用于产生具有不同的脉冲宽度的电源电压依赖性的脉冲信号，以执行预定的逻辑 基于来自输入转移检测脉冲发生块或脉冲宽度设定块的脉冲信号，通过逻辑运算部进行运算，从而输出对所使用的电源电压具有最佳的脉冲宽度的脉冲。 代替逻辑运算单元，通过使用控制信号输出具有任何脉冲宽度的脉冲，可以采用多种单元中的任意一个来选择输入转移检测脉冲生成块或脉冲宽度设定块的方法。 此外，输入转移脉冲产生块或脉冲宽度设置块可以被构造为基于通过使用RC延迟线产生的延迟时间来设置从其产生的脉冲的至少一个脉冲宽度。

公开(公告)号：US07433259B2

公开(公告)日：2008-10-07

申请号：US11507600

申请日：2006-08-22

申请人： Kimimasa Imai ,  Tomoaki Yabe

发明人： Kimimasa Imai ,  Tomoaki Yabe

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/002

摘要： A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

摘要翻译： 基本单元块具有多个存储单元，连接到多个存储单元的局部位线对，以及连接到本地位线对的位线预充电电路和传输门开关电路。 多个基本单元块中的局部位线对经由传输门开关电路连接到全局位线对。 全局位线对与局部位线对一起构成分层位线结构。 全局位线对布置成沿相同的方向延伸并且在该延伸方向上被扭转一次或多次。

公开(公告)号：US20080192527A1

公开(公告)日：2008-08-14

申请号：US12027548

申请日：2008-02-07

申请人： Tomoaki YABE

发明人： Tomoaki YABE

IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/412

摘要： A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括第一反相器和第二反相器，连接到第一反相器的输出端的第一存储节点和第二反相器的输入端，以及连接到第一反相器的第二存储节点 第一反相器的输入端子和第二反相器的输出端子，连接到存储单元的字线和分别连接到存储单元的多个位线。 输入数据被写入所选择的存储单元，并且在写入操作中从未选择的存储单元读取的数据被再次写入未选择的存储单元。

公开(公告)号：US20080089156A1

公开(公告)日：2008-04-17

申请号：US11872292

申请日：2007-10-15

申请人： Akihito Tohata ,  Tomoaki Yabe

发明人： Akihito Tohata ,  Tomoaki Yabe

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

摘要翻译： 一种半导体存储器件包括第一和第二单元阵列，其具有排列在行和列方向上的存储单元，连接到沿列方向排列的存储单元的第一和第二位线以及连接到列方向的第一和第二读出放大器 第一位，第二位线。 该装置还包括第一和第二虚拟单元阵列，其具有排列在行和列方向上的虚设单元，连接到沿行方向排列的虚拟单元的虚拟字线，连接到行方向的第一和第二虚拟位线 虚拟单元，沿列方向排列并接收来自虚拟字线的输出，以及第一和第二读出放大器激活电路，其根据从第一和第二虚拟位线输出的第一和第二控制信号激活第一，第二读出放大器 ， 分别。