公开(公告)号：US07863141B2

公开(公告)日：2011-01-04

申请号：US11492649

申请日：2006-07-25

Applicant: Jin Ping Liu

Inventor： Jin Ping Liu

IPC: H01L21/336

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848

Abstract: Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.

Abstract translation: 制造半导体器件的隔离区域的结构和方法。 示例方法包括以下。 我们在衬底中形成一个或多个掩埋掺杂区域。 我们在衬底上形成一个应力层。 我们在应力层上形成一个应变层。 我们通过应变层和应力层向下形成STI沟槽以至少部分地暴露掩埋的掺杂区域。 我们蚀刻掩埋的掺杂区域以形成至少与STI沟槽连通的掩埋腔。 在第一和第二实施例中，我们仅用绝缘材料填充STI沟槽以形成隔离区域并在空腔中形成空隙。 在第三和第四实施例中，我们用绝缘材料填充STI沟槽和空腔。

公开(公告)号：US20080121926A1

公开(公告)日：2008-05-29

申请号：US11464664

申请日：2006-08-15

Applicant: Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

Inventor： Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

IPC: H01L27/00

CPC classification number: H01L29/78 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L29/1054

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract translation: 集成电路系统包括衬底，衬底上的含碳的硅区域，衬底上的非含碳的硅区域和包含非含碳硅区域和碳 - 碳区域的硅 - 碳区域， 含硅区域。

公开(公告)号：US08652892B2

公开(公告)日：2014-02-18

申请号：US13113107

申请日：2011-05-23

Applicant: Jin Ping Liu ,  Judson Robert Holt

Inventor： Jin Ping Liu ,  Judson Robert Holt

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/4238 ,  H01L29/66636 ,  H01L29/7833

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

公开(公告)号：US08105955B2

公开(公告)日：2012-01-31

申请号：US11464664

申请日：2006-08-15

Applicant: Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

Inventor： Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

IPC: H01L21/31

CPC classification number: H01L29/78 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L29/1054

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract translation: 集成电路系统包括衬底，衬底上的含碳的硅区域，衬底上的非含碳的硅区域和包含非含碳硅区域和碳 - 碳区域的硅 - 碳区域， 含硅区域。

公开(公告)号：US20110223737A1

公开(公告)日：2011-09-15

申请号：US13113107

申请日：2011-05-23

Applicant: Jin Ping LIU ,  Judson Robert HOLT

Inventor： Jin Ping LIU ,  Judson Robert HOLT

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/4238 ,  H01L29/66636 ,  H01L29/7833

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract translation: 本发明的一些示例性实施例包括用于和半导体结构的方法，包括：源极/漏极区，栅极电介质，栅电极，沟道区的MOS晶体管; 碳掺杂的SiGe区域，其在沟道区域上施加应力，由此碳掺杂SiGe区域在随后的热处理之后在沟道区域上保持应力/应变。

公开(公告)号：US07947546B2

公开(公告)日：2011-05-24

申请号：US11502132

申请日：2006-08-09

Applicant: Jin Ping Liu ,  Judson Robert Holt

Inventor： Jin Ping Liu ,  Judson Robert Holt

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/4238 ,  H01L29/66636 ,  H01L29/7833

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract translation: 本发明的一些示例性实施例包括用于和半导体结构的方法，包括：源极/漏极区，栅极电介质，栅电极，沟道区的MOS晶体管; 碳掺杂的SiGe区域，其在沟道区域上施加应力，由此碳掺杂SiGe区域在随后的热处理之后在沟道区域上保持应力/应变。

公开(公告)号：US20080026540A1

公开(公告)日：2008-01-31

申请号：US11492649

申请日：2006-07-25

Applicant: Jin Ping Liu

Inventor： Jin Ping Liu

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848

Abstract: Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.

Abstract translation: 制造半导体器件的隔离区域的结构和方法。 示例方法包括以下。 我们在衬底中形成一个或多个掩埋掺杂区域。 我们在衬底上形成一个应力层。 我们在应力层上形成一个应变层。 我们通过应变层和应力层向下形成STI沟槽以至少部分地暴露掩埋的掺杂区域。 我们蚀刻掩埋的掺杂区域以形成至少与STI沟槽连通的掩埋腔。 在第一和第二实施例中，我们仅用绝缘材料填充STI沟槽以形成隔离区域并在空腔中形成空隙。 在第三和第四实施例中，我们用绝缘材料填充STI沟槽和空腔。

公开(公告)号：US20100308374A1

公开(公告)日：2010-12-09

申请号：US12857543

申请日：2010-08-16

Applicant: Jin Ping LIU ,  Alex KH SEE ,  Mei Sheng ZHOU ,  Liang Choo HSIA

Inventor： Jin Ping LIU ,  Alex KH SEE ,  Mei Sheng ZHOU ,  Liang Choo HSIA

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

Abstract: A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

Abstract translation: 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。

公开(公告)号：US20100109045A1

公开(公告)日：2010-05-06

申请号：US12262128

申请日：2008-10-30

Applicant: Jin Ping Liu ,  Yisuo Li ,  Alex K.H. See ,  Meisheng Zhou ,  Liang-Choo Hsia

Inventor： Jin Ping Liu ,  Yisuo Li ,  Alex K.H. See ,  Meisheng Zhou ,  Liang-Choo Hsia

IPC: H01L21/20 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: An integrated circuit system that includes: providing a substrate including an active device; forming a trench within the substrate adjacent the active device; forming a first layer with a first lattice constant within the trench; and forming a second layer with a second lattice constant over the first layer, the second lattice constant differing from the first lattice constant.

Abstract translation: 一种集成电路系统，包括：提供包括有源器件的衬底; 在邻近有源器件的衬底内形成沟槽; 在所述沟槽内形成具有第一晶格常数的第一层; 以及在所述第一层上形成具有第二晶格常数的第二层，所述第二晶格常数不同于所述第一晶格常数。

公开(公告)号：US20090146181A1

公开(公告)日：2009-06-11

申请号：US11952939

申请日：2007-12-07

Applicant: Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

Inventor： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

IPC: H01L29/778 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

Abstract translation: 一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。