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公开(公告)号：US4964142A
公开(公告)日：1990-10-16
申请号：US72955
申请日：1987-07-15
申请人： Kadiresan Annamalai
发明人： Kadiresan Annamalai
CPC分类号： H04J3/0632
摘要： Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.
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2.发明授权Emitter coupled logic having enhanced speed characteristic for turn-on and turn-off 失效发射极耦合逻辑具有增强的开启和关断速度特性
公开(公告)号：US4617478A
公开(公告)日：1986-10-14
申请号：US530176
申请日：1983-09-07
IPC分类号： H03K17/04 , H03K17/60 , H03K19/013 , H03K19/086 , H03K19/082 , H03K19/092
CPC分类号： H03K19/086 , H03K19/013
摘要： In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.
摘要翻译： 根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度 。 特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。 因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。 因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。
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公开(公告)号：US12131063B2
公开(公告)日：2024-10-29
申请号：US17219138
申请日：2021-03-31
发明人： Kevin M. Lepak
IPC分类号： G06F3/00 , G06F3/06 , G06F12/0882 , G06F12/1009
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0647 , G06F3/0679 , G06F12/0882 , G06F12/1009
摘要： Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality of memory management entries. In certain instances, the method includes generating a memory profile list, where the memory profile list includes a plurality of profile entries and each profile entry of the plurality of profile entries corresponding to a scanned memory management entry in the memory management structure.
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公开(公告)号：US12130741B2
公开(公告)日：2024-10-29
申请号：US18058534
申请日：2022-11-23
IPC分类号： G06F12/02 , G06F11/30 , G06F12/0871 , G06F12/0897
CPC分类号： G06F12/0871 , G06F11/3037 , G06F12/0246 , G06F12/0897 , G06F2212/401
摘要： Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression latency on system performance. To address the above issue, the proposed design takes advantage of the heavy compressors for effectively reducing memory bandwidth in high bandwidth memory (HBM) interfaces as long as they do not sacrifice system performance. Accordingly, the cache combines light and heavy compressors with a decision-making unit to achieve reduced off-chip memory traffic without sacrificing system performance.
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公开(公告)号：US12130692B2
公开(公告)日：2024-10-29
申请号：US17993562
申请日：2022-11-23
发明人： Karthik Rao , Indrani Paul , Donny Yi , Oleksandr Khodorkovsky , Leonardo De Paula Rosa Piga , Wonje Choi , Dana G. Lewis , Sriram Sambamurthy
IPC分类号： G06F1/32 , G06F1/3287
CPC分类号： G06F1/3287
摘要： An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
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公开(公告)号：US12130690B2
公开(公告)日：2024-10-29
申请号：US18316865
申请日：2023-05-12
发明人： Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC分类号： G06F1/32 , G06F1/3209 , G06F1/3234
CPC分类号： G06F1/3265 , G06F1/3209 , G06F1/3275
摘要： A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
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公开(公告)号：US20240354221A1
公开(公告)日：2024-10-24
申请号：US18760329
申请日：2024-07-01
IPC分类号： G06F11/36 , G06F8/41 , G06F16/23 , G06F16/245
CPC分类号： G06F11/3612 , G06F8/443 , G06F16/2379 , G06F16/245
摘要： Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).
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公开(公告)号：US20240345617A1
公开(公告)日：2024-10-17
申请号：US18603883
申请日：2024-03-13
CPC分类号： G06F1/08 , G06F1/12 , G06F9/505 , G06F11/3409
摘要： Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.
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公开(公告)号：US12118357B2
公开(公告)日：2024-10-15
申请号：US17855621
申请日：2022-06-30
CPC分类号： G06F9/30145 , G06F9/3838
摘要： The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12117945B2
公开(公告)日：2024-10-15
申请号：US17849117
申请日：2022-06-24
发明人： Hideki Kanayama , YuBin Yao
IPC分类号： G06F13/16
CPC分类号： G06F13/1689 , G06F13/1621 , G06F13/1642
摘要： A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.
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