-
1.发明公开公开(公告)号：US20240259024A1
公开(公告)日：2024-08-01
申请号：US18566749
申请日：2021-12-28
发明人： HIDEO YAMAJI , SHO OHASHI , YINTA LIN , RIICHI NISHINO , YOSHINORI TAKAHASHI
CPC分类号： H03L7/081 , H03L7/0891 , H03L7/091
摘要： In a circuit provided with a phase comparator, a lock time is shortened.
The phase comparator compares between a phase of a reference clock signal that has been input and a phase of a feedback clock signal, and outputs a comparison result. A charge pump generates a control voltage for control of a frequency of the feedback clock signal on the basis of the comparison result. A feedback unit generates the feedback clock signal in response to the control voltage. A stop detection unit detects whether or not the reference clock signal is stopped, and initializes the comparison result in a case where the reference clock signal is stopped.-
公开(公告)号：US12040806B2
公开(公告)日：2024-07-16
申请号：US18176339
申请日：2023-02-28
申请人： Kioxia Corporation
发明人： Masatomo Eimitsu
CPC分类号： H03L7/183 , H03L7/0891 , G11C7/222
摘要： A semiconductor integrated circuit includes an oscillation circuit and first and second current control circuits. The oscillation circuit includes a first series circuit having inverters, including a first inverter, connected in series and a second series circuit having inverters, including a second inverter, connected in series. An oscillation signal is output from the first series circuit. The first current control circuit is connected between a current source and an output terminal of the first inverter and configured to control a current from the current source into the first series circuit in accordance with a first signal synchronized with a clock signal. The second current control circuit is connected between an output terminal of the second inverter and a reference voltage node and configured to control a current from the second series circuit to the reference voltage node in accordance with a second signal synchronized with the clock signal.
-
公开(公告)号：US11968289B2
公开(公告)日：2024-04-23
申请号：US18088435
申请日：2022-12-23
发明人： Ki Hyun Pyun , Min Young Park , Jong Min Shim
CPC分类号： H04L7/033 , G09G3/32 , H03L7/0807 , H03L7/0891 , H03L7/095 , H03L7/099 , H04L7/041 , G09G2300/0857 , G09G2310/027 , G09G2310/08 , H03K19/21
摘要： A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.
-
4.发明授权公开(公告)号：US11967959B2
公开(公告)日：2024-04-23
申请号：US17861657
申请日：2022-07-11
发明人： Hsi-En Liu
CPC分类号： H03L7/0807 , H03L7/089 , H03L7/091
摘要： The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.
-
公开(公告)号：US20240088903A1
公开(公告)日：2024-03-14
申请号：US17931661
申请日：2022-09-13
发明人： Jia-Chi Samuel Chieh , Henry Ngo
CPC分类号： H03L7/0895 , H02M3/07
摘要： A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.
-
公开(公告)号：US11929753B1
公开(公告)日：2024-03-12
申请号：US17931661
申请日：2022-09-13
发明人： Jia-Chi Samuel Chieh , Henry Ngo
CPC分类号： H03L7/0895 , H02M3/07
摘要： A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.
-
公开(公告)号：US11804846B2
公开(公告)日：2023-10-31
申请号：US16674569
申请日：2019-11-05
CPC分类号： H03L7/0891 , H03L7/099
摘要： A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.
-
公开(公告)号：US11804845B2
公开(公告)日：2023-10-31
申请号：US17689649
申请日：2022-03-08
申请人： KANDOU LABS, S.A.
发明人： Armin Tajalli , Ali Hormati
CPC分类号： H03L7/0816 , H03L7/081 , H03L7/0807 , H03L7/089 , H03L7/0891 , H03L7/0896 , H03L7/093 , H03L7/0995 , H03L7/0998 , H03L7/23 , H03L2207/06
摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
-
公开(公告)号：US20230299672A1
公开(公告)日：2023-09-21
申请号：US17833847
申请日：2022-06-06
发明人： Jen-Chien Hsieh , TSUNG-YU WU
CPC分类号： H02M3/158 , H02M3/157 , H03L7/0891 , H02M1/08 , H03L7/099
摘要： A power converter device is provided. A feedback circuit outputs a comparison output signal. A phase-locked loop circuit provides a phase-locked signal according to a reference clock signal and an inductor voltage in a power converter circuit. An on-time circuit provides an on-time comparing signal according to the phase-locked signal, an input voltage, the inductor voltage and an output voltage of the power converter circuit. A first input terminal of an SR flip-flop receives the on-time comparing signal from the on-time circuit. A second input terminal of the SR flip-flop receives the comparison output signal from the feedback circuit. A frequency control circuit, according to changes in the input voltage and the output voltage of the power converter circuit, instantaneously adjusts the on-time of the on-time comparing signal such that an output terminal of the SR flip-flop outputs the adjusted on-time signal to the power converter circuit.
-
公开(公告)号：US11757613B2
公开(公告)日：2023-09-12
申请号：US17744743
申请日：2022-05-16
发明人： Chik Patrick Yue , Li Wang
IPC分类号： H03D3/18 , H03D3/24 , H04L7/00 , H03L7/081 , H03L7/08 , H03L7/089 , H04L27/06 , H04L43/087 , H03L7/099 , H03M1/46 , H03M7/16
CPC分类号： H04L7/0037 , H03L7/081 , H03L7/0807 , H03L7/0891 , H03L7/0995 , H04L7/0087 , H04L27/06 , H04L43/087 , H03M1/46 , H03M7/165
摘要： A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.
-
-
-
-
-
-
-
-
-
搜索结果
2285 条记录 (耗时 0.023 秒)
