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1.发明授权公开(公告)号：US12095471B2
公开(公告)日：2024-09-17
申请号：US17936505
申请日：2022-09-29
发明人： Bichoy Bahr , Yogesh Ramadass
CPC分类号： H03L7/0995 , H03B5/326 , H03H9/02244 , H03K3/0231 , H03L7/085 , H03M1/46
摘要： A clock circuit includes a voltage-controlled oscillator (VCO) having a control input and a first clock output. The clock circuit includes a frequency-locked loop (FLL) having an FLL input and a control output, the control output coupled to the control input. A microelectromechanical system (MEMS) resonator-based oscillator has a second clock output. A multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. The first multiplexer input is coupled to the first clock output. The second multiplexer input is coupled to the second clock output. The multiplexer output is coupled to the FLL input.
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公开(公告)号：US11990907B2
公开(公告)日：2024-05-21
申请号：US17954126
申请日：2022-09-27
IPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/03 , H03L7/099
CPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/0315 , H03L7/0992 , H03L7/0995
摘要： One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.
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公开(公告)号：US11949417B2
公开(公告)日：2024-04-02
申请号：US17838029
申请日：2022-06-10
摘要： Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
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公开(公告)号：US20240106442A1
公开(公告)日：2024-03-28
申请号：US17934654
申请日：2022-09-23
发明人： Jianjun YU , Yue CHAO , Tomas O'SULLIVAN , Lai Kan LEUNG
IPC分类号： H03L7/099 , H03B5/12 , H03K3/0231 , H03M1/46
CPC分类号： H03L7/099 , H03B5/1293 , H03K3/0231 , H03M1/46
摘要： Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.
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公开(公告)号：US20230253957A1
公开(公告)日：2023-08-10
申请号：US18010229
申请日：2021-06-15
发明人： Joseph B. BERNSTEIN , Ilan AHARON
IPC分类号： H03K3/0231 , H03K5/24 , H03K3/011 , H03K7/08
CPC分类号： H03K3/0231 , H03K5/2472 , H03K3/011 , H03K7/08
摘要： An integrated circuit is built with enhancement mode Gallium Nitride (GaN) components. The integrated circuit comprises a comparator circuit which compares an input voltage with a reference voltage to provide a controllable constant current source, the comparator having a drive transistor having a positive threshold voltage, the drive transistor being switched on and off based on a comparison result of the comparator. The circuit may drive ring oscillators and may provide pulse width modulation with variable duty cycle at constant frequency.
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公开(公告)号：US11705865B2
公开(公告)日：2023-07-18
申请号：US17846261
申请日：2022-06-22
发明人： Chi Cao , Kangmin Hu
IPC分类号： H03K3/0231 , H03B5/24
CPC分类号： H03B5/24 , H03K3/0231
摘要： The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal. The embodiment of the present disclosure eliminates the need to provide an additional common mode feedback generation circuit, and does not require an increase in power consumption, achieving the advantages of smaller occupied area, lower power consumption, less noise, and better performance as compared with a relaxation oscillator of the related art.
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公开(公告)号：US20230170884A1
公开(公告)日：2023-06-01
申请号：US18071162
申请日：2022-11-29
申请人： Open Silicon, Inc.
发明人： Santosh Mahadeo Narawade , Jithin K , Mohit Gupta
IPC分类号： H03K3/0231 , H03L7/099 , H03K3/03 , H03K5/133
CPC分类号： H03K3/0231 , H03L7/0995 , H03K3/0315 , H03K5/133
摘要： Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.
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公开(公告)号：US20220302906A1
公开(公告)日：2022-09-22
申请号：US17838029
申请日：2022-06-10
摘要： Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
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公开(公告)号：US11323067B2
公开(公告)日：2022-05-03
申请号：US17235270
申请日：2021-04-20
发明人： Masafumi Nakatani , Hiroki Murakami
IPC分类号： H03B5/04 , G05F3/26 , H03K3/0232 , H03K3/011 , H03K3/0231 , G05F1/573 , H03K5/135 , G05F1/56
摘要： The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.
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公开(公告)号：US11293891B2
公开(公告)日：2022-04-05
申请号：US16143897
申请日：2018-09-27
IPC分类号： G01N27/327 , G01N33/487 , G01N27/00 , H03K3/03 , G01N27/414 , G01N33/497 , H03K3/0231 , H03M1/60 , B82Y15/00
摘要： Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.
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