-
公开(公告)号：US20240322802A1
公开(公告)日：2024-09-26
申请号：US18583474
申请日：2024-02-21
发明人： Jean Camiolo , Geoffroy Godet
摘要： The present description concerns a derivative measurement circuit. The circuit implements successive cycles, each corresponding to a succession of first, second, and third periods of a clock signal. At each first period, an input voltage is memorized on a first capacitive element and the circuit delivers a voltage indicating a difference between a voltage on a second capacitive element and a voltage on a third capacitive element. At each second period, the input voltage is memorized on the second capacitive element and the circuit delivers a voltage indicating a difference between a voltage on the first capacitive element and the voltage on the third capacitive element. At each third period, the input voltage is memorized on the third capacitive element and the circuit delivers a voltage indicating a difference between the voltage on the second capacitive element and the voltage on the first capacitive element.
-
公开(公告)号：US11888482B2
公开(公告)日：2024-01-30
申请号：US17565110
申请日：2021-12-29
摘要： A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.
-
公开(公告)号：US11831314B1
公开(公告)日：2023-11-28
申请号：US17823655
申请日：2022-08-31
申请人： Apple Inc.
发明人： Simone del Cesta
CPC分类号： H03K3/011 , G05F3/245 , H03K3/023 , H03K3/0315 , H03L1/022
摘要： A ratiometric current source circuit having a reduced temperature dependence is disclosed. An embodiment of the current source circuit includes a first divider circuit configured to generate a reference voltage using a voltage level of a power supply node and a second divider circuit including a first resistor with a first temperature coefficient and a second resistor with a second temperature coefficient. The first resistor is configured to generate a first current using an input voltage and the voltage level of the power supply node and the second resistor is configured to generate a second current using the input voltage. The embodiment further includes a buffer circuit configured to generate the input voltage using the reference voltage and generate an output current using a difference between the first current and the second current.
-
公开(公告)号：US11557968B2
公开(公告)日：2023-01-17
申请号：US17184883
申请日：2021-02-25
发明人： Chen Kong Teh
摘要： According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.
-
公开(公告)号：US20220302903A1
公开(公告)日：2022-09-22
申请号：US17837960
申请日：2022-06-10
发明人： Chin-Ho CHANG , Jaw-Juinn HORING , Yung-Chow PENG
摘要： Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.
-
公开(公告)号：US11338144B2
公开(公告)日：2022-05-24
申请号：US16792102
申请日：2020-02-14
发明人： Edward K. F. Lee
摘要： A multiple output current stimulator circuit with fast turn on time is described. At least one pair of input side and output side transistors is arranged in a current mirror connected to a supply transistor by cascode coupling. The output side transistor supplies stimulation current to an electrode in contact with tissue. An operational amplifier connected to a reference voltage and to the output side transistor drives the supply transistor to maintain the voltage at the output side transistor equal to the reference voltage. The at least one pair of transistors includes multiple pairs of transistors whose output side transistors drive respective electrodes with stimulation currents. The stimulator determines the initiation and duration of stimulation current pulses supplied to each electrode. At circuit activation, large currents are generated which discharge capacitances in the output side transistors causing rapid output side transistor turn on.
-
公开(公告)号：US11106610B2
公开(公告)日：2021-08-31
申请号：US16570021
申请日：2019-09-13
发明人： Ying Duan , Shih-Wei Chou , Mansoor Basha Shaik , Harry Dang , Abhay Dixit
摘要： In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.
-
公开(公告)号：US20210226614A1
公开(公告)日：2021-07-22
申请号：US17301547
申请日：2021-04-06
申请人： Silanna Asia Pte Ltd
摘要： A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.
-
公开(公告)号：US20200321946A1
公开(公告)日：2020-10-08
申请号：US16375053
申请日：2019-04-04
申请人： Silanna Asia Pte Ltd
摘要： A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.
-
公开(公告)号：US10432207B2
公开(公告)日：2019-10-01
申请号：US15858591
申请日：2017-12-29
发明人： Douglas Alexander Robl , Brandon Robert Davis , Donald Lafrance , Joseph B. Zubah, Jr. , Mark Dickmann
摘要： An integrated circuit comprises an ADC including a first track-and-hold amplifier and a timing generator configured to generate a clock signal for controlling the ADC. The timing generator comprises a quadrature filter responsive to a differential input signal for generating a differential quadrature (I/Q) output signal. The timing generator further comprises at least one first vector sum circuit operatively coupled or connected to an output of the quadrature filter and configured to weight and sum components of the differential I/Q output signal for generating a clock signal having a desired delay.
-
-
-
-
-
-
-
-
-
搜索结果
203 条记录 (耗时 0.027 秒)
