公开(公告)号：US12117489B2

公开(公告)日：2024-10-15

申请号：US17019239

申请日：2020-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yung-Shun Chen ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Yung-Chow Peng

IPC: G01R31/317 ,  G01R27/26 ,  G01R31/10 ,  H03B27/00 ,  H03L7/00

CPC classification number: G01R31/31727 ,  G01R27/2605 ,  G01R27/2617 ,  G01R31/10 ,  H03B27/00 ,  H03L7/00

Abstract: A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.

公开(公告)号：US20220337257A1

公开(公告)日：2022-10-20

申请号：US17230863

申请日：2021-04-14

Applicant: NXP USA, Inc.

Inventor： Trevor Mark Newlin

IPC: H03L7/24 ,  H03B27/00 ,  H03L1/02

Abstract: A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

公开(公告)号：US11271710B1

公开(公告)日：2022-03-08

申请号：US17106483

申请日：2020-11-30

Applicant: Renesas Electronics America Inc.

Inventor： Ilhyun Cho ,  Kwang-Seok Han ,  Soonseob Lee ,  Heewon Suh ,  Gilpyo Lee

IPC: H04L7/00 ,  H03K3/012 ,  H03B27/00 ,  H03H7/21

Abstract: A quadrature phase clock generator includes a tunable polyphase filter and a phase detector. The tunable polyphase filter is configured to receive an input clock signal and generate four quadrature phase clock signals. The phase detector is coupled to receive at least two of the four quadrature phase clock signals and generate a control signal adapted to tune the polyphase filter based on the received quadrature phase clock signals. Further, the phase detector is configured to provide the control signal to the polyphase filter in a feedback loop. Based on the control signal from the phase detector, the tunable polyphase filter generates four tuned quadrature phase clock signals as output phase clock signals.

公开(公告)号：US10910997B2

公开(公告)日：2021-02-02

申请号：US16639933

申请日：2017-09-19

Applicant: Mitsubishi Electric Corporation

Inventor： Akihito Hirai ,  Mitsuhiro Shimozawa

IPC: H03B27/00 ,  H03B5/12 ,  H03L7/099 ,  H03L7/24

Abstract: A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

公开(公告)号：US10884449B2

公开(公告)日：2021-01-05

申请号：US16404032

申请日：2019-05-06

Applicant: QUALCOMM Incorporated

Inventor： Alireza Khalili ,  Mohammad Emadi ,  Shahram Abdollahi-Alibeik ,  Ali Mostajeran

IPC: G06F1/08 ,  H03B27/00 ,  H03D7/14 ,  H03D7/16 ,  G06K1/04 ,  H03K21/02 ,  H03K5/01

Abstract: An LO clock signal generator includes a fundamental mixer for mixing a source clock signal with a divided version of the source clock signal. The LO clock signal generator also includes a harmonic mixer for mixing the source clock signal with a third harmonic of a divided version of the source clock signal.

公开(公告)号：US10715159B2

公开(公告)日：2020-07-14

申请号：US16397204

申请日：2019-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-seog Kim ,  Sang-soo Ko ,  Byoung-joong Kang

IPC: H03L7/24 ,  H03L7/00 ,  H03L7/099 ,  H03B27/00 ,  H03L5/02 ,  H04B1/403 ,  H03K5/156 ,  H03K21/02 ,  H03K21/10 ,  H03L7/10 ,  H03K21/17

Abstract: A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

公开(公告)号：US10476660B1

公开(公告)日：2019-11-12

申请号：US16155512

申请日：2018-10-09

Applicant: Micron Technology, Inc.

Inventor： Liuchun Cai ,  Steven G. Wurzer ,  Gregory A. King

IPC: H04B1/26 ,  H04B7/00 ,  H04L7/04 ,  H03H7/21 ,  H03B27/00 ,  H03L7/06

Abstract: Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

公开(公告)号：US10382015B2

公开(公告)日：2019-08-13

申请号：US15611496

申请日：2017-06-01

Applicant: City University of Hong Kong

Inventor： Quan Xue ,  Liang Wu

IPC: H03B5/12 ,  H03K3/03 ,  H03B27/00

Abstract: Systems and methods which provide oscillator configurations implementing phase rotation (rotated-phase-tuning (RPT)) are described. Embodiments of a RPT oscillator may employ phase interpolation, whereby two current vectors having different phases are superimposed to provide a resultant current vector having a tunable phase to vary a phase shift in a feedback loop of an oscillator circuit and correspondingly tune the oscillation frequency. Phase rotation provided by an RPT oscillator configuration of embodiments inserts a negative phase shift (rotation phase shift) into each of two current branches to rotate the phase shifts of a phase-tuning technique, such as for avoiding phase ambiguity with respect to tunable oscillation frequencies. RPT oscillators of embodiments are varactor-less and are particularly well suited for operation to provide output frequencies in the millimeter-wave (mmW) band.

公开(公告)号：US10164573B2

公开(公告)日：2018-12-25

申请号：US15094163

申请日：2016-04-08

Applicant: UNIVERSITE DE NICE ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Gilles Fernand Jacquemod ,  Emeric De Foucauld ,  Alexandre Benjamin Fonseca ,  Yves Leduc ,  Philippe Bernard Pierre Lorenzini

IPC: H03B27/00 ,  H03K17/16 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0948 ,  H01L29/78 ,  H03K3/03 ,  H03K19/0944

Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.

公开(公告)号：US20180097478A9

公开(公告)日：2018-04-05

申请号：US15436582

申请日：2017-02-17

Applicant: Washington University

Inventor： Jr-Shin Li ,  Anatoly Zlotnik

IPC: H03B27/00 ,  G01R29/08

CPC classification number: H03B27/00

Abstract: A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2π-periodic control signal v(θ) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.