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    CONTACT GATE ISOLATION
    2.
    发明申请
    CONTACT GATE ISOLATION 有权

    公开(公告)号：US20250063792A1

    公开(公告)日：2025-02-20

    申请号：US18526473

    申请日：2023-12-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chu-Yuan HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250056838A1

    公开(公告)日：2025-02-13

    申请号：US18584688

    申请日：2024-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seo Woo Nam ,  Heon Jong Shin ,  Jae Ran Jang

    IPC: H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device comprises a back insulating pattern comprising a first region, and a second region and extending in a first direction, a plurality of sheet patterns disposed on the back insulating pattern, and extending in the first direction, a first source/drain pattern disposed on the first region of the back insulating pattern, and connected to the plurality of sheet patterns, a second source/drain pattern disposed on the second region of the back insulating pattern, and connected to the plurality of sheet patterns, a gate electrode extending in a second direction crossing the first direction, and surrounding the plurality of sheet patterns, a first back source/drain contact that extends into the first region of the back insulating pattern, and connected to the first source/drain pattern and a second back source/drain contact that extends into the second region of the back insulating pattern, and connected to the second source/drain pattern.

    Semiconductor storage device
    5.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US12225719B2

    公开(公告)日：2025-02-11

    申请号：US17524369

    申请日：2021-11-11

    Applicant: Socionext Inc.

    Inventor： Yasumitsu Sakai

    IPC: H10B20/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

    METHOD FOR MAKING COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPERLATTICE ISOLATION LAYER
    8.
    发明申请
    METHOD FOR MAKING COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPERLATTICE ISOLATION LAYER 有权

    公开(公告)号：US20250048718A1

    公开(公告)日：2025-02-06

    申请号：US18790385

    申请日：2024-07-31

    Applicant: ATOMERA INCORPORATED

    Inventor： DONGHUN KANG ,  MAREK HYTHA

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

    Abstract: A method for making a semiconductor device may include forming a plurality of complimentary field effect transistors (CFETs). Each CFET may include an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, with each of the NFET and PFET including spaced apart source and drain regions defining respective channels therebetween. Each CFET may further include a gate overlying both of the channels, and at least one isolation layer between the NFET and the PFET. The at least one isolation layer may include a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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