-
公开(公告)号：US20240362060A1
公开(公告)日：2024-10-31
申请号：US18655004
申请日：2024-05-03
发明人： Matthew FELLOWS , Annette CHEN , Leandra IRVINE
CPC分类号： G06F9/466 , G06F9/30094 , G06F9/544
摘要： A banking pipeline for processing various transactions for multiple financial instruments is disclosed herein. The pipeline may have three distinct interpreters, a transaction interpreter, a rollup interpreter, and a rules interpreter. Different aspects of the transaction may be performed on separate interpreters and each interpreter may perform its aspect of the transaction before the next interpreter begins.
-
公开(公告)号：US12131190B2
公开(公告)日：2024-10-29
申请号：US17180514
申请日：2021-02-19
发明人： Carla L. Christensen , Reshmi Basu
CPC分类号： G06F9/5016 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F11/3024 , G06F11/3433 , H04L67/10 , H04L67/535
摘要： Methods, systems, and apparatuses related to management of a computing device usage profile are described. The usage profile can be a usage profile of a computing device. Characteristics of workloads executed by a computing device can be monitored to determine whether performance of the computing device can be optimized by execution of an updated usage profile. Responsive to a determination that the performance of the computing device can be improved by execution of an updated usage profile, the updated usage profile can be received by the computing device and executed thereon.
-
公开(公告)号：US20240345956A1
公开(公告)日：2024-10-17
申请号：US18754499
申请日：2024-06-26
IPC分类号： G06F12/0811 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/54 , G06F11/30 , G06F12/0808 , G06F12/0815 , G06F12/0817 , G06F12/0831 , G06F12/084 , G06F12/0895 , G06F12/128 , G06F13/16
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30047 , G06F9/30079 , G06F9/3867 , G06F9/467 , G06F9/544 , G06F9/546 , G06F11/3037 , G06F12/0808 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/084 , G06F12/0895 , G06F12/128 , G06F13/1668 , G06F2212/1021 , G06F2212/608
摘要： An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.
-
4.发明公开公开(公告)号：US20240338372A1
公开(公告)日：2024-10-10
申请号：US18748448
申请日：2024-06-20
IPC分类号： G06F16/2455 , G06F9/46
CPC分类号： G06F16/24568 , G06F9/467
摘要： Aspects described herein may relate to a transaction exchange platform using a streaming data platform (SDP) and microservices to process transactions in accordance with corresponding workflows. The transaction exchange platform may receive transactions from origination sources, which may be added to the SDP as transaction objects. Microservices on the transaction exchange platform may interact with the transaction objects based on configured workflows associated with the transactions. Further, the microservices may leverage machine-learning models to determine whether transaction objects may be more effectively processed using alternative or secondary workflows. Processing on the transaction exchange platform may facilitate clearing and settlement of transactions. Some aspects may provide for dynamic and flexible reconfiguration of workflows.
-
公开(公告)号：US20240338242A1
公开(公告)日：2024-10-10
申请号：US18575122
申请日：2022-06-29
申请人： ARTIFRIENDS INC.
发明人： Jung Woo LEE
IPC分类号： G06F9/46
CPC分类号： G06F9/466
摘要： A method of improving a processing speed of a transaction in a blockchain network includes steps of loading data necessary for transaction processing in a bundle in advance onto the blockchain network according to a type of transaction presented by a client before execution of a smart contract, storing data to be stored in a bundle in the blockchain network according to a type of transaction to be processed after execution of the smart contract on the data loaded in the bundle, and performing bundled processing in units of blocks on the stored data without individually processing the transaction to be processed.
-
公开(公告)号：US12113361B2
公开(公告)日：2024-10-08
申请号：US18338962
申请日：2023-06-21
CPC分类号： H02J3/003 , G06F9/5094 , H02J3/14 , H02J3/144 , G06F2209/5019 , G06F2209/504 , G06F2209/506 , H02J2203/20 , H02J2310/60 , H02J2310/62
摘要： Disclosed techniques relate to orchestrating power consumption reductions across a number of hosts. A number of response levels may be utilized, each having an association to a corresponding set of reduction actions. The impact to customers, hosts, and/or workloads can be computed at run time based on current and/or predicted conditions and workloads, and a particular response level can be selected based on the computed impact. These techniques enable a sufficient, but least impactful response to be employed.
-
公开(公告)号：US12112197B2
公开(公告)日：2024-10-08
申请号：US17953821
申请日：2022-09-27
发明人： Michael John Livesley , Ian King , Alistair Goudie
CPC分类号： G06F9/4881 , G06F9/462
摘要： A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
-
公开(公告)号：US12099882B2
公开(公告)日：2024-09-24
申请号：US17494495
申请日：2021-10-05
IPC分类号： G06F9/46 , G06F9/4401 , G06F9/48 , G06F9/50 , G06N7/01
CPC分类号： G06F9/5072 , G06F9/4401 , G06F9/4881 , G06F9/5077 , G06N7/01
摘要： Techniques are disclosed for deploying a computing resource (e.g., a service) in response to user input. A computer-implemented method can include operations of identifying a first set of computing components already deployed within the cloud-computing environment and identifying a second set of computing components available for deployment within the cloud-computing environment. A request for deployment may be subsequently received for one of the available computing components. A bootstrap request corresponding to the particular computing component requested may be transmitted to a deployment orchestrator, the deployment orchestrator being configured to deploy the particular computing component to the cloud-computing environment based at least in part on the bootstrap request. A user interface may present status indicators for each computing component (e.g., deployed, available, requested, etc.).
-
公开(公告)号：US12099867B2
公开(公告)日：2024-09-24
申请号：US15993061
申请日：2018-05-30
CPC分类号： G06F9/4881
摘要： Systems, apparatuses, and methods for implementing a multi-kernel wavefront scheduler are disclosed. A system includes at least a parallel processor coupled to one or more memories, wherein the parallel processor includes a command processor and a plurality of compute units. The command processor launches multiple kernels for execution on the compute units. Each compute unit includes a multi-level scheduler for scheduling wavefronts from multiple kernels for execution on its execution units. A first level scheduler creates scheduling groups by grouping together wavefronts based on the priority of their kernels. Accordingly, wavefronts from kernels with the same priority are grouped together in the same scheduling group by the first level scheduler. Next, the first level scheduler selects, from a plurality of scheduling groups, the highest priority scheduling group for execution. Then, a second level scheduler schedules wavefronts for execution from the scheduling group selected by the first level scheduler.
-
公开(公告)号：US20240311235A1
公开(公告)日：2024-09-19
申请号：US18673628
申请日：2024-05-24
IPC分类号： G06F11/10 , G06F9/30 , G06F9/38 , G06F9/448 , G06F9/46 , G06F9/48 , G06F9/52 , G06F12/0811 , G06F12/0815 , G06F12/0879 , G06F12/0888 , G06F12/0895 , G06F12/128 , G06F13/16 , H03M13/15
CPC分类号： G06F11/106 , G06F9/30047 , G06F9/30101 , G06F9/3867 , G06F9/4498 , G06F9/467 , G06F9/4812 , G06F9/52 , G06F11/1064 , G06F11/1068 , G06F12/0811 , G06F12/0879 , G06F12/0895 , G06F13/1668 , H03M13/1575 , G06F12/0815 , G06F12/0888 , G06F12/128 , G06F2212/1024 , G06F2212/1028 , G06F2212/1032 , G06F2212/608
摘要： An example device includes a first memory that store a first set of data; a second memory that stores a second set of data that includes a stored error correcting code (ECC) value; and a controller coupled to the first memory and to the second memory. The controller operates to receive a transaction directed to the first set of data, and based on the transaction perform the following operations: retrieve the second set of data from the second memory; calculate a current ECC value based on the second set of data as retrieved from the second memory; compare the stored ECC value to the current ECC value to determine whether the second set of data includes an error; determine whether the error is correctable; and determine not to access the first memory to perform the transaction based on a determination that the second set of data includes the non-correctable error.
-
-
-
-
-
-
-
-
-
搜索结果
30037 条记录 (耗时 0.042 秒)
