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公开(公告)号：US11966814B2
公开(公告)日：2024-04-23
申请号：US18101522
申请日：2023-01-25
申请人： Google LLC
发明人： Craig Gidney , Austin Greig Fowler
IPC分类号： G11C11/40 , G06F7/48 , G06F7/505 , G06F7/72 , G06F17/10 , G06N10/00 , G11C11/4063 , H04B10/70
CPC分类号： G06N10/00 , G06F7/4824 , G06F7/505 , G06F7/5057 , G06F7/72 , G06F17/10 , G11C11/4063 , H04B10/70
摘要： Methods and apparatus for performing surface code computations using Auto-CCZ states. In one aspect, a method for implementing a delayed choice CZ operation on a first and second data qubit using a quantum computer includes: preparing a first and second routing qubit in a magic state; interacting the first data qubit with the first routing qubit and the second data qubit with the second routing qubit using a first and second CNOT operation, where the first and second data qubits act as controls for the CNOT operations; if a received first classical bit represents an off state: applying a first and second Hadamard gate to the first and second routing qubit; measuring the first and second routing qubit using Z basis measurements to obtain a second and third classical bit; and performing classically controlled fixup operations on the first and second data qubit using the second and third classical bits.
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公开(公告)号：US20230385233A1
公开(公告)日：2023-11-30
申请号：US18446357
申请日：2023-08-08
发明人： Thomas A. Volpe , Sundeep Amirineni , Thomas Elmer
CPC分类号： G06F15/8046 , G06F7/53 , G06F7/5443 , G06F7/505 , G06F9/3001
摘要： Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.
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公开(公告)号：US20230281497A1
公开(公告)日：2023-09-07
申请号：US18111413
申请日：2023-02-17
申请人： Google LLC
发明人： Craig Gidney
CPC分类号： G06N10/00 , G06F7/4824 , G06F7/505 , G06F7/5057 , G06F7/72 , G06F17/10 , G11C11/4063 , H04B10/70
摘要： Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.
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公开(公告)号：US11620106B1
公开(公告)日：2023-04-04
申请号：US17123194
申请日：2020-12-16
发明人： Makia S Powell
摘要： A combined adder for N logical bits to produce a sum from a first addend having N first addend bits and a second addend having N second addend bits. A least significant adder produces a segment sum of the least significant bits and a carry out. Segment adder pairs are used for each higher order of significant sums. One segment adder produces a segment sum portion, and the other produces an incremented segment sum portion. Carry logic associated with each segment is utilized with a multiplexer to select the incremented segment sum portion or the segment sum portion. The selected segment sum portions are assembled with a most significant carry out to produce the sum.
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公开(公告)号：US11568298B2
公开(公告)日：2023-01-31
申请号：US16833301
申请日：2020-03-27
申请人： Google LLC
发明人： Craig Gidney , Austin Greig Fowler
IPC分类号： G11C11/00 , G06N10/00 , G11C11/4063 , G06F7/48 , G06F7/72 , G06F7/505 , G06F17/10 , H04B10/70
摘要： Methods and apparatus for performing surface code computations using Auto-CCZ states. In one aspect, a method for implementing a delayed choice CZ operation on a first and second data qubit using a quantum computer includes: preparing a first and second routing qubit in a magic state; interacting the first data qubit with the first routing qubit and the second data qubit with the second routing qubit using a first and second CNOT operation, where the first and second data qubits act as controls for the CNOT operations; if a received first classical bit represents an off state: applying a first and second Hadamard gate to the first and second routing qubit; measuring the first and second routing qubit using Z basis measurements to obtain a second and third classical bit; and performing classically controlled fixup operations on the first and second data qubit using the second and third classical bits.
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公开(公告)号：US20210132906A1
公开(公告)日：2021-05-06
申请号：US17120077
申请日：2020-12-11
申请人： SHANGHAI UNIVERSITY
发明人： Yi JIN , Yunfu SHEN , Shan OUYANG , Junjie PENG , Junjie ZHANG , Hongjian WANG
摘要： Disclosed is a method for configuring an MSD parallel adder based on ternary logic operators. Five ternary logic operators that satisfy a sufficient condition for MSD addition are used to configure an MSD parallel adder. During the arrangement of a ternary logic operator, any method in the following may be used: each of ternary operators of n bits is reconfigured into a ternary logic operator each time, and reconfiguration is performed five times for implementation; each of ternary operators of n bits is reconfigured into two ternary logic operators having the same input each time, and reconfiguration is performed three times for implementation; each of ternary operators of n bits is reconfigured into five ternary logic operators of the same time, and reconfiguration is performed once for implementation; corresponding unreconfigurable ternary logic operators are used instead for the foregoing reconfiguration process.
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公开(公告)号：US10963221B2
公开(公告)日：2021-03-30
申请号：US16802966
申请日：2020-02-27
发明人： Daniel Pugh , Raymond Nijssen
IPC分类号： G06F7/533 , H03K19/17728 , G06F7/505
摘要： In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.
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公开(公告)号：US20200311592A1
公开(公告)日：2020-10-01
申请号：US16833250
申请日：2020-03-27
申请人： Google LLC
发明人： Craig Gidney
摘要： Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.
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9.发明申请公开(公告)号：US20200211907A1
公开(公告)日：2020-07-02
申请号：US16810937
申请日：2020-03-06
发明人： Min-Chul Sun , Myeong-Cheol KIM , Kyoung-Sub SHIN
IPC分类号： H01L21/8238 , G06F7/505 , H01L23/535 , H01L29/06 , H01L29/08 , H01L29/10 , H01L27/092 , H01L21/308 , H01L21/306 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/417 , G06F30/398 , G06F30/39
摘要： In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.
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公开(公告)号：US20200210146A1
公开(公告)日：2020-07-02
申请号：US16237104
申请日：2018-12-31
发明人： Fabio Indelicato
摘要： An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.
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